JackHammer: Efficient Rowhammer on Heterogeneous FPGA-CPU Platforms (1912.11523v3)

Abstract: After years of development, FPGAs are finally making an appearance on multi-tenant cloud servers. These heterogeneous FPGA-CPU architectures break common assumptions about isolation and security boundaries. Since the FPGA and CPU architectures share hardware resources, a new class of vulnerabilities requires us to reassess the security and dependability of these platforms. In this work, we analyze the memory and cache subsystem and study Rowhammer and cache attacks enabled on two proposed heterogeneous FPGA-CPU platforms by Intel: the Arria 10 GX with an integrated FPGA-CPU platform, and the Arria 10 GX PAC expansion card which connects the FPGA to the CPU via the PCIe interface. We show that while Intel PACs currently are immune to cache attacks from FPGA to CPU, the integrated platform is indeed vulnerable to Prime and Probe style attacks from the FPGA to the CPU's last level cache. Further, we demonstrate JackHammer, a novel and efficient Rowhammer from the FPGA to the host's main memory. Our results indicate that a malicious FPGA can perform twice as fast as a typical Rowhammer attack from the CPU on the same system and causes around four times as many bit flips as the CPU attack. We demonstrate the efficacy of JackHammer from the FPGA through a realistic fault attack on the WolfSSL RSA signing implementation that reliably causes a fault after an average of fifty-eight RSA signatures, 25% faster than a CPU rowhammer attack. In some scenarios our JackHammer attack produces faulty signatures more than three times more often and almost three times faster than a conventional CPU rowhammer attack.

• The paper introduces JackHammer, an FPGA-based Rowhammer attack demonstrating enhanced efficiency and stealth compared to traditional CPU methods on integrated FPGA-CPU systems.
• JackHammer achieves significantly higher bit flip rates (up to 4x) and faster fault induction (e.g., 25% faster RSA signature faults) by leveraging the FPGA's high memory throughput.
• The findings highlight critical security vulnerabilities on integrated FPGA-CPU platforms, emphasizing the need for new defensive strategies like hardware monitoring and improved cache coherency.

Efficient Rowhammer on Heterogeneous FPGA-CPU Platforms

The paper "JackHammer: Efficient Rowhammer on Heterogeneous FPGA-CPU Platforms" addresses the emerging security concerns associated with the increasing integration of Field-Programmable Gate Arrays (FPGAs) into CPU architectures, especially within multi-tenant cloud servers. The authors focus on how this integration creates novel attack vectors, particularly exposing hardware vulnerabilities such as the Rowhammer effect, which is exacerbated by the high-speed memory access capabilities of FPGAs.

Overview

The work examines two Intel FPGA-CPU systems—the integrated Arria 10 GX with CPU package integration and the Arria 10 GX PAC expansion card connected via PCIe—highlighting how these establish new pathways for attacks. The authors identify significant differences in vulnerability between these platforms, noting that while the PAC card is generally immune, the integrated platform is susceptible to cache and memory attacks. They have meticulously reverse-engineered memory and cache interfaces to uncover potential exploits.

The researchers introduce JackHammer, an FPGA-based Rowhammer attack that leverages the superior memory throughput of the FPGA. The FPGA can generate twice the hammering speed and quadruple the bit flips compared to traditional CPU-based Rowhammer attacks. Their experiments show that JackHammer is capable of inducing faults through Rowhammer attacks much more efficiently and stealthily than previous methods, seeing as it bypasses CPU microarchitecural detection systems. The results from JackHammer are practically showcased through fault attacks on RSA implementations, specifically targeting the WolfSSL library, where the attack significantly speeds up the generation of corrupted RSA signatures.

Strong Numerical Results

The authors deliver convincing quantitative results demonstrating the attack's potency. JackHammer operating from an FPGA induces bit flips around four times more frequently than CPU attacks in comparable scenarios. The attack is 25% faster at causing RSA signature faults on average, and, in some cases, JackHammer produces results three times faster than CPU-based approaches. Such metrics underscore the potential risks posed to systems utilizing integrated FPGA-CPU architecture without adequate defenses.

Implications and Future Directions

The paper's findings necessitate a reconsideration of security strategies on hybrid FPGA-CPU systems. The vulnerabilities in cache coherency and row access, particularly in shared-public environments like cloud services, emphasize the need for new detection methodologies and protections. Hardware monitoring, cache partitioning, and row refresh rate adjustments are discussed as potential defensive measures against exploited weak points.

Looking forward, the authors offer speculation on further vulnerabilities and countermeasures as FPGA technology becomes more prevalent in server configurations. The insights call for continual exploration into how increased FPGA functionality may necessitate novel security paradigms beyond those employed for traditional CPUs.

Conclusion

JackHammer presents an inclement reality for multi-tenant architectures integrating FPGA and CPU systems. The paper poses crucial insights into how enhancements in architectural flexibility through FPGAs also invite severe security ramifications. It makes a compelling case for further research and adaptation in designing robust defenses capable of mitigating such powerful hardware-based exploits.