Store-to-Leak Forwarding: Leaking Data on Meltdown-resistant CPUs (Updated and Extended Version) (1905.05725v2)

Abstract: Meltdown and Spectre exploit microarchitectural changes the CPU makes during transient out-of-order execution. Using side-channel techniques, these attacks enable leaking arbitrary data from memory. As state-of-the-art software mitigations for Meltdown may incur significant performance overheads, they are only seen as a temporary solution. Thus, software mitigations are disabled on more recent processors, which are not susceptible to Meltdown anymore. In this paper, we show that Meltdown-like attacks are still possible on recent CPUs which are not vulnerable to the original Meltdown attack. We show that the store buffer - a microarchitectural optimization to reduce the latency for data stores - in combination with the TLB enables powerful attacks. We present several ASLRrelated attacks, including a KASLR break from unprivileged applications, and breaking ASLR from JavaScript. We can also mount side-channel attacks, breaking the atomicity of TSX, and monitoring control flow of the kernel. Furthermore, when combined with a simple Spectre gadget, we can leak arbitrary data from memory. Our paper shows that Meltdown-like attacks are still possible, and software fixes are still necessary to ensure proper isolation between the kernel and user space. This updated extended version of the original paper includes new results and explanations on the root cause of the vulnerability and shows how it is different to MDS attacks like Fallout.

• The paper reveals that store-to-load forwarding vulnerabilities enable data leakage in CPUs deemed secure against Meltdown, challenging existing defenses.
• It introduces three attack techniques—Data Bounce, Fetch+, and Speculative Fetch+—which exploit store buffers and TLB state to infer memory mappings and code usage.
• The findings emphasize the need for rethinking CPU design and mitigation strategies to secure transient execution paths and improve data isolation.

Store-to-Leak Forwarding: An Analysis of Vulnerabilities in Recent CPUs

The paper "Store-to-Leak Forwarding: Leaking Data on Meltdown-resistant CPUs (Updated and Extended Version)" presents a critical examination of continuing vulnerabilities in contemporary CPUs, despite various mitigations aimed at protecting against attacks like Meltdown and Spectre. The authors, Schwarz et al., explore how certain microarchitectural features, namely the store buffer combined with TLB implementations, still permit data leakage on CPUs that are ostensibly impervious to the original Meltdown attack.

Overview of Key Findings

The researchers provide compelling evidence that Meltdown-like attacks remain viable by exploiting store-to-load forwarding mechanisms in CPUs. They introduce three core attack techniques: Data Bounce, Fetch+, and Speculative Fetch+, each with distinct operational levels and implications:

1. Data Bounce leverages the store buffer's reliance on a fully resolved physical address for load forwarding to determine if a virtual address is backed by physical memory. This mechanism proficiently breaches ASLR systems by recognizing valid mappings without leaving architectural traces.
2. Fetch+ extends Data Bounce by integrating TLB state evaluations. It discerns whether an address was recently accessed, offering insights into data and code usage without direct memory access.
3. Speculative Fetch+ takes advantage of speculative execution to encode leakable data within TLB states, independent of shared cache memory, thus facilitating Spectre-style attacks without traditional dependencies.

Implications of This Research

The discoveries in this paper highlight ongoing security vulnerabilities in microarchitectural optimizations intended to enhance CPU performance. Despite the deployment of hardware and software defenses against Meltdown and Spectre vulnerabilities, the store buffer remains a vector for sophisticated attacks that compromise data isolation principles.

From a practical standpoint, these findings urge the reconsideration of current mitigations and encourage further exploration of secure CPU design that can adequately separate user and kernel space interactions. On a theoretical level, the research modifies our understanding of transient execution side channels, revealing potential oversight in existing safeguarding measures.

Future Directions

Future research should aim to strengthen the isolation between various levels of CPU operations to prevent unintended data sharing. Moreover, advancements in speculative execution mechanisms should be explored to mitigate these vulnerabilities without degrading system performance. There is also a need for developing detection systems that can identify and address these side-channel attacks in real time, prioritizing a balance between security and performance optimization.

Conclusion

Schwarz et al.'s extensive investigation into the effects of store-to-load forwarding reveals significant security gaps in modern CPUs that must be addressed to ensure robust protection against Meltdown-like side-channel attacks. This work underscores the importance of revisiting and refining CPU architecture to fortify systems against covert data exposure threats, inspiring a critical reevaluation of both existing and upcoming security solutions in processor design.