FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge (1904.04421v1)

Abstract: While embedded FPGAs are attractive platforms for DNN acceleration on edge-devices due to their low latency and high energy efficiency, the scarcity of resources of edge-scale FPGA devices also makes it challenging for DNN deployment. In this paper, we propose a simultaneous FPGA/DNN co-design methodology with both bottom-up and top-down approaches: a bottom-up hardware-oriented DNN model search for high accuracy, and a top-down FPGA accelerator design considering DNN-specific characteristics. We also build an automatic co-design flow, including an Auto-DNN engine to perform hardware-oriented DNN model search, as well as an Auto-HLS engine to generate synthesizable C code of the FPGA accelerator for explored DNNs. We demonstrate our co-design approach on an object detection task using PYNQ-Z1 FPGA. Results show that our proposed DNN model and accelerator outperform the state-of-the-art FPGA designs in all aspects including Intersection-over-Union (IoU) (6.2% higher), frames per second (FPS) (2.48X higher), power consumption (40% lower), and energy efficiency (2.5X higher). Compared to GPU-based solutions, our designs deliver similar accuracy but consume far less energy.

FPGA/DNN Co-Design Methodology for Enhanced IoT Intelligence

The paper presents a simultaneous FPGA/DNN co-design methodology tailored for deep neural networks (DNNs) aiming to maximize efficiency on resource-constrained embedded FPGA platforms. Specifically targeting edge devices in IoT applications, this method integrates top-down and bottom-up approaches to concurrently design DNN models and their corresponding FPGA accelerators, achieving optimized performance in terms of latency, power consumption, and energy efficiency, without compromising accuracy.

Methodology Overview

The proposed methodology encompasses two primary approaches: a bottom-up hardware-oriented DNN model search, and a top-down FPGA accelerator design that incorporates DNN-specific characteristics. The bottom-up approach involves the construction of DNN models that inherently consider hardware limitations from the onset. The top-down approach focuses on FPGA design, leveraging the insights from the DNN models to optimize for specific tasks.

Four key components drive the co-design methodology:

1. Bundle-Arch: A hardware-aware DNN template that guides DNN construction from fundamental building blocks known as Bundles.
2. Auto-DNN: An automated search engine that efficiently explores the design space for DNN models under predefined constraints.
3. Tile-Arch: A low-latency FPGA accelerator architecture template promoting resource reuse and pipeline optimization.
4. Auto-HLS: An automatic generator that produces synthesizable C code for developing board-level FPGA designs.

The synergy between Auto-DNN and Auto-HLS facilitates an iterative process for refining DNN and FPGA designs through continuous updates based on accuracy, power, and latency metrics.

Results

The paper demonstrates the effectiveness of the co-design approach in an object detection task using a PYNQ-Z1 FPGA, which adheres to the stringent conditions outlined by the Design Automation Conference System Design Contest. Compared to a top-down approach, the proposed method achieved:

• A 6.2% improvement in accuracy measured by Intersection-over-Union (IoU).
• A 2.48× increase in frames per second (FPS).
• Power consumption reduced by 40%.
• Energy efficiency improved by 2.5×.

When matched against GPU-based solutions, the designed FPGA architectures delivered competitive accuracy levels, alongside significantly lower energy consumption—highlighting the practicality of employing FPGA accelerators in energy-sensitive environments.

Implications and Future Directions

The implications of this research are substantial for applications requiring rapid and efficient execution of DNN models on IoT devices. Its ability to enhance hardware design processes opens avenues for deploying complex machine learning models on edge devices with constrained resources. Furthermore, the automatic generation of FPGA designs through Auto-HLS holds potential to accelerate machine learning integration across varying platforms.

Theoretical advancements could stem from further refinement of Bundle templates, incorporating more sophisticated DNN constructs while retaining hardware efficiency. Practically, expanding this co-design framework to support an even broader array of IoT applications could foster a more universally adaptable solution for DNN deployment.

Moving forward, exploring the extension of co-design methodologies for other hardware platforms and architectures could yield comprehensive strategies essential for continuing advancements in AI. Furthermore, incorporating AI-driven approaches into the co-design process might provide novel optimizations unattainable through traditional means.

In conclusion, this paper's co-design methodology stands as a robust approach for reconciling the demands of DNN performance with the limitations inherent in FPGA devices, evidencing its potential to drive forward the integration of AI functionalities into constrained IoT environments.