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Architectures for High Performance Computing and Data Systems using Byte-Addressable Persistent Memory (1805.10041v1)

Published 25 May 2018 in cs.DC and cs.AR

Abstract: Non-volatile, byte addressable, memory technology with performance close to main memory promises to revolutionise computing systems in the near future. Such memory technology provides the potential for extremely large memory regions (i.e. > 3TB per server), very high performance I/O, and new ways of storing and sharing data for applications and workflows. This paper outlines an architecture that has been designed to exploit such memory for High Performance Computing and High Performance Data Analytics systems, along with descriptions of how applications could benefit from such hardware.

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Authors (4)
  1. Adrian Jackson (24 papers)
  2. Michele Weiland (64 papers)
  3. Mark Parsons (5 papers)
  4. Bernhard Homoelle (2 papers)
Citations (5)

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