A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs) (1708.04198v2)

Abstract: Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multi-core neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.

• The paper presents a novel multi-core routing scheme that combines hierarchical and mesh strategies to optimize event-driven neural communication.
• It integrates heterogeneous memory types, such as asynchronous SRAM, CAM, and emerging RRAM, to enhance in-memory processing efficiency.
• A prototype fabricated in 0.18 µm CMOS demonstrates low-latency performance and energy efficiency for real-time neuromorphic applications.

Overview of "A Scalable Multi-core Architecture with Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)"

The research paper presents an advanced design of a neuromorphic processor architecture, focusing on optimizing event-driven communication in spiking neural networks. The paper outlines a novel routing scheme integrated into a multi-core processor, which combines hierarchical and mesh routing aligned with heterogeneous memory structures. This design is aimed at minimizing memory usage and latency while preserving the flexibility required to support diverse event-based neural network architectures.

Architectural Design

The proposed architecture incorporates a sophisticated routing methodology that blends hierarchical and mesh strategies. Two key types of routers—R1, R2, and R3—are employed to manage intra-core, inter-core, and inter-chip communication. The architecture optimizes event-driven communication by combining point-to-point and multi-cast routing schemes, significantly reducing memory consumption. This is in contrast to previous architectures that either constrained connectivity for efficiency or employed excessive memory resources for broader configurability.

Heterogeneous Memory Structures

The design exploits a variety of memory types, including asynchronous SRAM and CAM, integrated within neuron and synapse arrays. This approach aligns with the trend towards distributed in-memory computing, where the memory and processing resources are co-localized—critical in mitigating bottlenecks associated with von Neumann architectures. The utilization of emerging RRAM technology is also suggested as an avenue for future memory optimization.

Neuromorphic Processor Prototype

The DYNAPs architecture is validated with a prototype chip, featuring four cores comprising 1k analog neurons, and demonstrates a notable advancement in power efficiency and low-latency communication. The processor is fabricated using a mixed-signal approach in a 0.18 µm CMOS process, achieving power consumption figures comparable to state-of-the-art fully digital counterparts. The design supports complex neural models, including convolutional neural networks (CNNs), with a configurable neuron interconnectivity that suits real-time applications.

Theoretical Contributions and Implications

The routing scheme presented provides a theoretically grounded solution to the trade-offs between memory demands and network flexibility. It introduces a two-stage route optimization influenced by biological neural network patterns, effectively balancing memory use with functional connectivity.

The proposed architecture pushes forward the implementation of large-scale neuromorphic systems, particularly in energy-efficient devices for real-time sensing and processing. Future applications could span autonomous robotics, real-time data streams, and AI systems requiring rapid, local computation.

Future Directions

Advancement to more scaled semiconductor processes and integration of advanced memory technologies could yield additional gains in capacity and efficiency. Moreover, continued exploration of bio-inspired structures may refine scalability and broaden application domains for neuromorphic computing.

Overall, this research presents a significant contribution to the development of scalable, efficient neuromorphic systems by addressing key challenges in routing architectures and memory management. This work sets a foundation for future innovations in harnessing the potential of neuromorphic computing to address complex computational tasks effectively.