Steep-slope Hysteresis-free Negative Capacitance MoS2 Transistors (1704.06865v2)

Abstract: The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of integration in a junctionless transistor topology, offer enhanced electrostatic control of the channel. Here, we combine these two advantages and demonstrate for the first time a molybdenum disulfide (MoS2) 2D steep slope transistor with a ferroelectric hafnium zirconium oxide layer (HZO) in the gate dielectric stack. This device exhibits excellent performance in both on- and off-states, with maximum drain current of 510 {\mu}A/{\mu}m, sub-thermionic subthreshold slope and is essentially hysteresis-free. Negative differential resistance (NDR) was observed at room temperature in the MoS2 negative capacitance field-effect-transistors (NC-FETs) as the result of negative capacitance due to the negative drain-induced-barrier-lowering (DIBL). High on-current induced self-heating effect was also observed and studied.

• The paper demonstrates a MoS2-based NC-FET that integrates a 20 nm HZO layer to achieve a sub-thermionic 6 mV/dec slope and a maximum drain current of 510 μA/μm.
• Methodology involves exfoliation and precise deposition with rapid thermal annealing to achieve robust capacitance matching and hysteresis-free behavior.
• The findings pave the way for ultra-low power, high-speed transistor designs, offering significant potential for mobile computing and energy-efficient electronics.

An Overview of "Steep Slope Hysteresis-free Negative Capacitance MoS2 Transistors"

The paper presents a significant advancement in the ongoing research focused on overcoming the limitations imposed by the Boltzmann Tyranny in MOSFETs through the integration of ferroelectric layers and two-dimensional (2D) materials. Specifically, the authors demonstrate a molybdenum disulfide (MoS2) negative capacitance field-effect transistor (NC-FET) with ferroelectric hafnium zirconium oxide (HZO), exhibiting excellent electrostatic control and hysteresis-free operation.

Key Findings and Methodology

The authors address the subthreshold slope (SS) challenge by incorporating a 20 nm thick HZO layer within the gate stack of a MoS2-based transistor. This inclusion results in a maximum drain current (I_D) of 510 μA/μm, significantly surpassing conventional MoS2 transistors using a 90 nm SiO2 dielectric. The device achieves a sub-thermionic SS of 6 mV/dec in a nominally hysteresis-free manner, thereby allowing lower power operation at elevated speeds.

The experimental devices were fabricated through a combination of exfoliation and physical deposition methods, involving the placement of mono to multi-layer MoS2 as the channel material atop an engineered gate stack. This stack consists of a 2 nm amorphous Al2O3 layer for capacitance matching and leakage minimization beneath the HZO layer. Remarkably, the devices exhibit no significant hysteresis effect, attributed to careful control over the rapid thermal annealing (RTA) process of the ferroelectric layer.

Quantitative Insights

Density measurements indicate that the fabricated devices maintain a drain-induced barrier lowering (DIBL) attributed to negative capacitance effects, manifesting in a negative differential resistance (NDR) at off-state. This observation is consistent with the theoretical predictions, indicating the reverse impact of ferroelectric materials on traditional DIBL trends observed in bulk CMOS technologies.

Moreover, temperature-dependent analyses reveal that the SS remains sub-thermionic down to approximately 220 K, above which Schottky barrier influences become predominant. Notably, the absence of apparent substrate thickness dependence in SS across a varying MoS2 layer count signifies robustness in the capacitance matching scheme employed.

Theoretical and Practical Implications

The results put forth in this paper have multiple implications. Theoretically, the successful integration of 2D MoS2 in a hysteresis-free configuration using negative capacitance challenges the current understanding of SS limitations in semiconductor physics. Practically, these developments present a roadmap for implementing ultra-low power, high-speed transistors in next-generation electronic devices.

The reduction in power dissipation while maintaining robust on-off current performance opens new avenues for applications in mobile computing and energy-efficient systems. Additionally, the findings encourage further investigations into the intrinsic limits of ferroelectric material performance when scaled to sub-5 nm channel lengths.

Future Perspectives

Continued research efforts in this domain may focus on enhancing the thermal management of NC-FETs, given the observed self-heating phenomena under high current densities. Moreover, optimizing the integration techniques for large-area fabrication and examining alternate ferroelectric compounds could push these device architectures closer to industrial application thresholds.

In conclusion, this paper successfully integrates ferroelectric layers with 2D materials, unveiling critical insights that bridge experimental and theoretical advances in the design of next-generation transistors. The work serves as a pivotal point in the development of low power, high-performance electronic devices, poised to meet the demands of ever-evolving technology landscapes.