Computing in Memory with Spin-Transfer Torque Magnetic RAM (1703.02118v4)

Abstract: In-memory computing is a promising approach to addressing the processor-memory data transfer bottleneck in computing systems. We propose Spin-Transfer Torque Compute-in-Memory (STT-CiM), a design for in-memory computing with Spin-Transfer Torque Magnetic RAM (STT-MRAM). The unique properties of spintronic memory allow multiple wordlines within an array to be simultaneously enabled, opening up the possibility of directly sensing functions of the values stored in multiple rows using a single access. We propose modifications to STT-MRAM peripheral circuits that leverage this principle to perform logic, arithmetic, and complex vector operations. We address the challenge of reliable in-memory computing under process variations by extending ECC schemes to detect and correct errors that occur during CiM operations. We also address the question of how STT-CiM should be integrated within a general-purpose computing system. To this end, we propose architectural enhancements to processor instruction sets and on-chip buses that enable STT-CiM to be utilized as a scratchpad memory. Finally, we present data mapping techniques to increase the effectiveness of STT-CiM. We evaluate STT-CiM using a device-to-architecture modeling framework, and integrate cycle-accurate models of STT-CiM with a commercial processor and on-chip bus (Nios II and Avalon from Intel). Our system-level evaluation shows that STT-CiM provides system-level performance improvements of 3.93x on average (upto 10.4x), and concurrently reduces memory system energy by 3.83x on average (upto 12.4x).

Overview of Spin-Transfer Torque Magnetic RAM for In-Memory Computing

The paper presents an innovative approach to addressing the processor-memory bottleneck through the development of a Spin-Transfer Torque Compute-in-Memory (STT-CiM) architecture utilizing Spin-Transfer Torque Magnetic RAM (STT-MRAM). This research advances the field of in-memory computing by leveraging the unique properties of spintronic memory, which facilitates the computation of logic and arithmetic functions within the memory array itself, thus minimizing the need for data transfer between processor and memory.

Key Contributions

The authors provide several contributions that distinguish their approach:

1. In-Memory Logic and Arithmetic Operations: By simultaneously activating multiple wordlines in an STT-MRAM array, the design allows for the computation of bitwise and arithmetic operations such as OR, AND, XOR, and addition directly within the memory array. This ability is rooted in STT-MRAM's resistive nature, which supports direct sensing of function outputs from enabled wordlines.
2. Reliability under Process Variations: To ensure reliable computations despite process-induced variations, the authors extend traditional error correction codes (ECC) to STT-CiM operations. The proposed error detection and correction techniques are shown to be effective in maintaining the integrity of in-memory operations.
3. Integration and System-Level Evaluation: The paper further addresses the integration of STT-CiM within a general-purpose computing architecture by proposing extensions to the processor instruction sets and modifications to on-chip buses. These enhancements enable STT-CiM to function as a scratchpad memory, thereby delivering significant system-level performance improvements—averaging 3.93x speedup—and energy reductions—averaging 3.83x.
4. Data Mapping and Vector Operations: The research introduces novel data mapping strategies and vector compute-in-memory (VCiM) operations, which utilize the wider internal memory bandwidth to facilitate efficient parallel data processing. These enhancements demonstrate substantial gains, particularly in data-parallel workloads.

Research Implications and Future Directions

The integration of STT-CiM within computing systems represents a potential shift in addressing memory bottlenecks by fundamentally altering data access patterns. The implications are vast both theoretically, as it proposes an architecture co-design with emerging memory technologies, and practically, as it reduces energy consumption and enhances throughput.

Future research could expand upon this work by exploring further optimization of ECC schemes specific to various STT-MRAM configurations, as well as extending the range of operations supported by in-memory computing. Additionally, a deeper exploration of hybrid memory systems combining STT-MRAM with other non-volatile memory technologies might yield further benefits in terms of performance, cost, and scalability.

Concluding Thoughts

In summary, this paper presents an intriguing advancement in the field of memory technologies and its integration into computing systems. By transforming the role of memory within the system architecture itself, the authors posit a potential avenue for significant improvements in computation efficiency. Moreover, their work sets a robust foundation for future explorations into the possibilities offered by non-volatile memory technologies in supporting next-generation computing paradigms.