Analyzing the Carrier Mobility in Transition-metal Dichalcogenide MoS2 Field-effect Transistors (1701.02079v1)

Abstract: Transition-metal dichalcogenides (TMDCs) are important class of two-dimensional (2D) layered materials for electronic and optoelectronic applications, due to their ultimate body thickness, sizable and tunable bandgap, and decent theoretical room-temperature mobility of hundreds to thousands cm2/Vs. So far, however, all TMDCs show much lower mobility experimentally because of the collective effects by foreign impurities, which has become one of the most important limitations for their device applications. Here, taking MoS2 as an example, we review the key factors that bring down the mobility in TMDC transistors, including phonons, charged impurities, defects, and charge traps. We introduce a theoretical model that quantitatively captures the scaling of mobility with temperature, carrier density and thickness. By fitting the available mobility data from literature over the past few years, we are able to obtain the density of impurities and traps for a wide range of transistor structures. We show that interface engineering such as oxide surface passivation, high-k dielectrics and BN encapsulation could effectively reduce the impurities, leading to improved device performances. For few-layer TMDCs, we analytically model the lopsided carrier distribution to elucidate the experimental increase of mobility with the number of layers. From our analysis, it is clear that the charge transport in TMDC samples is a very complex problem that must be handled carefully. We hope that this Review can provide new insights and serve as a starting point for further improving the performance of TMDC transistors.

• The paper develops a transport model using the Boltzmann Transport Equation and relaxation time approximation to analyze intrinsic and extrinsic scattering effects.
• It demonstrates that acoustic phonon scattering dominates at low temperatures while optical phonons prevail at higher temperatures, with extrinsic factors reducing experimental mobility.
• Interface engineering strategies such as high-k dielectrics and h-BN encapsulation significantly mitigate Coulomb impurity and trap effects to enhance mobility.

Analyzing Carrier Mobility in MoS2 Transition-Metal Dichalcogenide Field-Effect Transistors

The paper undertakes an examination of the factors affecting carrier mobility in field-effect transistors (FETs) incorporating transition-metal dichalcogenide (TMDC) materials, particularly MoS2. The work addresses the persistent challenge wherein the experimental mobility of TMDCs underperforms relative to theoretical estimates due to extrinsic factors including impurities, defects, and charge traps.

Key Findings and Analysis

The authors have developed a theoretical transport model employing the Boltzmann Transport Equation (BTE) and the relaxation time approximation to analyze the mobility of charge carriers in monolayer MoS2 under various conditions. By adjusting for different scattering mechanisms—acoustic and optical phonons, Coulomb impurities (CIs), and charge traps—the paper endeavors to appropriately fit experimental mobility data from a wide range of FETs documented in the literature.

Electron-Phonon Scattering

The researchers quantify intrinsic phonon scattering limits, demonstrating that scatterings by acoustic phonons are preeminent at low temperatures while optical phonons dominate at higher temperatures. They cite theoretical estimates that situate maximum mobility at ~410 cm²Vs⁻¹ under room temperature when unhindered by extrinsic scattering agents.

Extrinsic Scattering and Interface Engineering

Extrinsic scattering, primarily from CIs at interfaces and charge traps originating from defects, significantly deteriorates mobility. The paper indicates varying responses; the dielectric environment modulates CI scattering potential, while charge traps influence both transport regimes and induce metal-to-insulator transitions. The paper highlights high-k dielectrics and h-BN encapsulation as viable interface engineering remedies, with notable success in mitigating CI scattering.

Few-layer MoS2 and Mobility Optimization

The paper expands its model to few-layer MoS2 configurations, acknowledging changes in electron distribution lopsidedness and implications for charge carrier scattering. The analysis demonstrates enhanced mobility in thicker TMDC films, attributable to reduced secondary interface influence and carrier screening. The authors acknowledge that mobility is further improved in heterostructures with superior interface qualities like double-sided h-BN encapsulation, corroborating a reduction in CI and trap levels.

Implications and Future Directions

The comprehensive modeling strategy elucidates a methodology for diagnosing and mitigating mobility bottlenecks in TMDCs, underlining the profound impact of material interfaces on electronic properties. The insights gleaned are significant for optimizing transistor design beyond silicon technology, especially as the industry pursues continued device scaling and Moore’s law progression.

Emerging areas for further exploration include enhancing material synthesis to reduce intrinsic defect levels and investigating the TMD/CMOS technology interface for better heterointegration. Another prospective trajectory is exploring the intrinsic limits of these materials, potentially through refined synthesis and encapsulation techniques that can accommodate quantum-level effects and foster applications in quantum devices.

In conclusion, while the persisting issue of low experimental mobility in TMDCs is complex, it is clear that meticulous interface engineering and improved understanding of electron environments can propel TMDCs closer to their theoretical potential, facilitating the advancement of next-generation electronic devices.