Silicon CMOS architecture for a spin-based quantum computer (1609.09700v1)

Abstract: Recent advances in quantum error correction (QEC) codes for fault-tolerant quantum computing \cite{Terhal2015} and physical realizations of high-fidelity qubits in a broad range of platforms \cite{Kok2007, Brown2011, Barends2014, Waldherr2014, Dolde2014, Muhonen2014, Veldhorst2014} give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based entirely on complementary metal-oxide-semiconductor (CMOS) technology, which is the basis for all modern processor chips. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin states of a single electron confined in a quantum dot, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout \cite{Colless2013}. This system, based entirely on available technology and existing components, is compatible with general surface code quantum error correction \cite{Terhal2015}, enabling large-scale universal quantum computation.

• The paper demonstrates a silicon CMOS architecture that seamlessly integrates spin qubits in quantum dots with transistor-based control circuitry on a single chip.
• It employs gate-based dispersive readout and tunable exchange couplings to enable parallel qubit control with power dissipation as low as 50 nW per unit cell.
• The approach leverages mature CMOS technology to offer a scalable pathway for fabricating large quantum processors and advancing fault-tolerant quantum computing.

Overview of the Silicon CMOS Architecture for a Spin-Based Quantum Computer

The paper "Silicon CMOS architecture for a spin-based quantum computer" by Veldhorst et al. proposes a novel architecture for quantum computing that leverages silicon-based complementary metal-oxide-semiconductor (CMOS) technology. The architecture is presented as a potential solution to the challenge of scaling quantum processors to include millions of qubits while maintaining a feasible classical-quantum interface, a notable limitation in current quantum computing systems.

Key Contributions and Methodology

The paper highlights a silicon-based quantum processor design where qubits are defined by electron spin states confined in quantum dots, and operations are controlled using a transistor-based control circuit integrated into the same silicon chip. This approach benefits from the inherent advantages of CMOS technology, known for scalability and high integration density in classical computing, suggesting that existing foundries could potentially fabricate such processors with continued advances in technology.

Key components of the proposed architecture include:

1. Quantum Dot Qubits: Defined by single electron spins in a two-dimensional array, offering a dense and scalable configuration controlled by tunable magnetic fields and exchange couplings.
2. Control Circuitry: Implementation of a CMOS-based control circuit that operates qubits through charge-storage electrodes, enabling parallel addressing and qubit stabilization techniques similar to those used in DRAM technology.
3. Qubit Control and Readout: Utilizes scalable data lines to tune qubit resonance frequencies and exchange couplings, allowing for both global and individual qubit control. Measurement is performed via gate-based dispersive readout, conducive to high-fidelity operations within qubit coherence times.

The architecture underscores an important concept: the compatibility of quantum dot qubits with CMOS technology, potentially allowing large-scale integration using currently available and emerging semiconductor technology.

Numerical Results and Claims

The authors emphasize that the architecture achieves scalability by integrating both classical control circuits and quantum circuits on a single silicon-on-insulator (SOI) wafer. Of particular significance is the detailed calculation of power dissipation, estimating a power requirement of approximately 50 nW per surface code unit cell. This estimation is crucial, given that efficient heat dissipation is a significant barrier in designing large-scale quantum systems.

Implications and Future Directions

Practically, this proposed architecture could allow for an economically viable path to fabricating large quantum processors by integrating current silicon fabrication capabilities with quantum technologies. This integration would not only minimize costs but also potentially accelerate the development timeline for practical quantum computing applications.

On a theoretical level, the paper provides a structured foundation for exploring spin-based quantum computing within a scalable, dense platform, leveraging the highest-fidelity silicon qubits. The move towards using spin qubits underscores the importance of error thresholds in quantum error correction, with fault tolerance being an achievable target as qubit fidelity improves.

Future research may focus on improving the uniformity and reproducibility of devices. These enhancements could further reduce the number of control transistors required per qubit, making real-world implementations more feasible. Furthermore, the architecture may be adapted for other quantum systems, broadening its applicability beyond silicon-based platforms.

In conclusion, this work delineates a clear pathway toward scalable quantum computing solutions, rooted firmly in existing technological frameworks. Its emphasis on compatibility with CMOS technology opens up interesting dialogues about the direction of quantum processor development and the role of traditional semiconductor technologies in supporting emerging quantum computing paradigms.