A Design of a Fast Parallel-Pipelined Implementation of AES: Advanced Encryption Standard (1501.01427v1)

Abstract: The Advanced Encryption Standard (AES) algorithm is a symmetric block cipher which operates on a sequence of blocks each consists of 128, 192 or 256 bits. Moreover, the cipher key for the AES algorithm is a sequence of 128, 192 or 256 bits. AES algorithm has many sources of parallelism. In this paper, a design of parallel AES on the multiprocessor platform is presented. While most of the previous designs either use pipelined parallelization or take advantage of the Mix_Column parallelization, our design is based on combining pipelining of rounds and parallelization of Mix_Column and Add_Round_Key transformations. This model is divided into two levels: the first is pipelining different rounds, while the second is through parallelization of both the Add_Round_Key and the Mix_Column transformations. Previous work proposed for pipelining AES algorithm was based on using nine stages, while, we propose the use of eleven stages in order to exploit the sources of parallelism in both initial and final round. This enhances the system performance compared to previous designs. Using two-levels of parallelization benefits from the highly independency of Add_Round_Key and Mix_Column/ Inv_Mix_Colum transformations. The analysis shows that the parallel implementation of the AES achieves a better performance. The analysis shows that using pipeline increases significantly the degree of improvement for both encryption and decryption by approximately 95%. Moreover, parallelizing Add_Round_Key and Mix_Column/ Inv_Mix_Column transformations increases the degree of improvement by approximately 98%. This leads to the conclusion that the proposed design is scalable and is suitable for real-time applications.

• The paper introduces a dual-level parallel pipelined design that exploits both inter-round and intra-round parallelism to significantly enhance AES performance.
• The methodology employs an 11-stage pipeline and parallel execution of Mix_Column and Add_Round_Key, achieving encryption and decryption speed improvements of approximately 95% to 98%.
• The design's enhanced scalability and efficiency make it ideal for real-time applications in multiprocessor environments, with promising implications for future hardware optimizations.

Overview of the Parallel-Pipelined Implementation of AES

The paper, authored by Ghada F. Elkabbany, Heba K. Aslan, and Mohamed N. Rasslan, presents a parallel-pipelined design for implementing the Advanced Encryption Standard (AES) algorithm on a multiprocessor platform. This research proposes an enhanced approach by integrating pipelining with parallelization specifically for the Mix_Column and Add_Round_Key transformations. Notably, the AES algorithm is structurally versatile to accommodate different bit lengths of 128, 192, or 256, both for the blocks and key sequence.

Design Approach and Innovations

The authors introduce a dual-level parallelization model. The first level involves pipelining different AES rounds, extending traditional nine-stage designs to eleven stages. This encompasses parallelism in both the initial and final rounds, which prior designs did not fully exploit. The second level achieves parallelism within rounds through the decomposition and parallel execution of Add_Round_Key and Mix_Column transformations. The approach leverages the inherent independency between these transformations to significantly enhance execution speed.

Numerical Results

Empirical evaluations indicate substantial performance improvements. Specifically, the parallel implementation enhances encryption and decryption speeds by approximately 95% and achieves additional improvements close to 98% when Add_Round_Key and Mix_Column transformations are separately parallelized. Moreover, the proposed 11-stage pipeline architecture demonstrated improved scalability and efficiency compared to traditional nine-stage implementations.

Implications and Future Directions

The practical implications of this design are significant for applications requiring real-time data processing, such as high-frequency financial transactions or time-sensitive communications. The enhanced parallel structure and execution efficiency present AES as a robust cryptographic standard suitable for scalable multiprocessor environments.

Further exploration of various hardware configurations and the refinement of parallelization techniques may yield even higher efficiencies and broader applicability. Future studies might focus on optimizing key generation processes and investigating impacts on energy consumption for large-scale deployments.

Overall, this research contributes to the ongoing development of more efficient cryptographic implementations, addressing both theoretical and practical challenges in high-performance computing environments.