Stochastic Testing Method for Transistor-Level Uncertainty Quantification Based on Generalized Polynomial Chaos (1409.4831v1)

Abstract: Uncertainties have become a major concern in integrated circuit design. In order to avoid the huge number of repeated simulations in conventional Monte Carlo flows, this paper presents an intrusive spectral simulator for statistical circuit analysis. Our simulator employs the recently developed generalized polynomial chaos expansion to perform uncertainty quantification of nonlinear transistor circuits with both Gaussian and non-Gaussian random parameters. We modify the nonintrusive stochastic collocation (SC) method and develop an intrusive variant called stochastic testing (ST) method to accelerate the numerical simulation. Compared with the stochastic Galerkin (SG) method, the resulting coupled deterministic equations from our proposed ST method can be solved in a decoupled manner at each time point. At the same time, ST uses fewer samples and allows more flexible time step size controls than directly using a nonintrusive SC solver. These two properties make ST more efficient than SG and than existing SC methods, and more suitable for time-domain circuit simulation. Simulation results of several digital, analog and RF circuits are reported. Since our algorithm is based on generic mathematical models, the proposed ST algorithm can be applied to many other engineering problems.

• The paper presents a novel stochastic testing method that leverages generalized polynomial chaos to quantify transistor-level uncertainty in integrated circuits.
• The method decouples deterministic equations using adaptive time-stepping, significantly reducing testing nodes and computational overhead.
• Practical simulations on RF circuits and SRAM cells validate the approach, demonstrating marked speedup and accuracy compared to traditional stochastic methods.

Stochastic Testing Method for Transistor-Level Uncertainty Quantification Based on Generalized Polynomial Chaos

The paper under review presents a significant advancement in the domain of uncertainty quantification (UQ) for integrated circuit (IC) design, emphasizing the need for efficient simulation techniques. The authors introduce an intrusive spectral simulator employing generalized polynomial chaos (gPC) expansion to accomplish transistor-level UQ, addressing both Gaussian and non-Gaussian uncertainties.

A salient feature of this work lies in the development of the Stochastic Testing (ST) method, an improvement upon existing stochastic solvers like stochastic Galerkin (SG) and stochastic collocation (SC). Unlike the SG method, which solves a coupled system of deterministic equations, or the SC approach, which requires numerous sampling points for numerical integration, the ST method optimizes computational efficiency by decoupling the deterministic equations at each time point. This decoupling is achieved by utilizing fewer testing nodes, which facilitates flexible time step management, thereby making the ST method particularly suitable for time-domain simulation of nonlinear circuits.

The underlying mathematical framework utilizes the versatile gPC to handle a broader class of uncertainties beyond Gaussian measures. The primary contributions of the ST method that distinguish it from previous approaches are:

1. Intrusive Simulator Design: The authors propose an intrusive framework where the analysis is based on solving a larger dimension coupled deterministic equation without prior decoupling. This is unlike the previous nonintrusive adaptations of stochastic collocation.
2. Efficient Node Selection: ST employs a novel approach for testing node selection, allowing it to use significantly fewer nodes compared to the traditional SC methods, which often rely on tensor product or sparse grid rules.
3. Adaptability in Simulation: By permitting adaptive time-stepping controls within an intrusive simulation environment, ST delivers remarkable speedup over SG, maintaining accuracy with reduced computational overhead.

The implications of this work extend notably into practical applications of EDA tools, facilitating more rapid and accurate circuit simulations under stochastic conditions. The results demonstrated through various examples, including RF circuits and digital systems like the SRAM cell, indicate ST's efficacy in handling real-world circuit complexities efficiently.

Simulation case studies reveal that the ST method achieves a speedup factor that can be highly beneficial especially in transient simulations, where adaptive time-stepping further aligns computational effort with dynamic precision requirements. Moreover, the paper exhibits that the speedup factor can be particularly notable when confronting high-dimensional problems or higher-order polynomial chaos expansions.

The contributions of this research reinforce the prospect of applying stochastic solvers not only within RNG frameworks to obtain statistical estimates but also directly tackling dynamic system behavior in uncertain contexts. Future developments could extend this exploration to incorporate more complex models of variability and explore potential parallel implementations to further leverage computational resources efficiently.

In essence, the proposed method represents a substantial advancement in the computational techniques available for transistor-level UQ in IC design, offering a robust blend of efficiency and accuracy that could significantly influence future research aims in circuit simulation and electronic design automation.