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Efficient FPGA-based multipliers for F_{3^97} and F_{3^{6*97}} (0708.3022v1)
Published 22 Aug 2007 in cs.CR
Abstract: In this work we present a new structure for multiplication in finite fields. This structure is based on a digit-level LFSR (Linear Feedback Shift Register) multiplier in which the area of digit-multipliers are reduced using the Karatsuba method. We compare our results with the other works in the literature for F_{397}. We also propose new formulas for multiplication in F_{3{6*97}}. These new formulas reduce the number of F_{397}-multiplications from 18 to 15. The fields F_{3{97}} and F_{3{6*97}} are relevant in the context of pairing-based cryptography.