---
title: Variable Adaptive Readout Chip (AARDVARC)
url: https://www.emergentmind.com/topics/variable-adaptive-readout-chip-aardvarc
type: topic
---

# Variable Adaptive Readout Chip (AARDVARC)

The Variable Adaptive Readout Chip (AARDVARC) is a high-speed, multi-channel system-on-a-chip waveform digitizer platform designed for precision photon detection applications, particularly in conjunction with Large Area Picosecond Photodetectors (LAPPDs). Developed by Nalu Scientific, AARDVARC is engineered to provide sub-nanosecond timing resolution, deep on-chip buffering, and highly configurable readout, supporting large-scale physics experiments such as Cherenkov and scintillation light-based neutrino detection [2511.22765].

## 1. Architecture and Core Design Features

AARDVARC integrates four independent analog input channels per chip, with prototype revisions supporting up to eight channels. Each channel is equipped with a broadband, low-noise transimpedance preamplifier (TIA), providing an analog bandwidth greater than 1.6 GHz (−3 dB). The inputs are AC-coupled using on-chip transformers or capacitors. An independent discriminator/comparator with a programmable threshold per channel facilitates flexible trigger generation.

The core sampling employs a switched-capacitor array (SCA) architecture with a depth of 32,768 samples per channel. Each SCA cell utilizes a precision metal-insulator-metal capacitor followed by a MOS track/hold switch. Sampling rates are dynamically controllable between 10 and 14 GSa/s, corresponding to 100–71 ps per sample. Clock signals are provided by on-chip phase-locked loop (PLL) or delay-locked loop (DLL) circuits, maintaining clock jitter below 5 ps RMS and intra-chip channel skew under 1 ps.

Analog signals are digitized using a ramp-compare ADC with 12 bits of resolution per sample. Digitization can be limited to a region of interest (ROI) for efficient event-focused readout. Typical dynamic range extends to approximately 1 Vpp, with integral non-linearity (INL) below 0.15 % over 750 mV (extending to ≈1 V with active linearity correction). Quantization noise is theoretically ~0.29 LSB RMS (≈70 µV).

A deep circular buffer per channel maintains 32 k samples, supporting post-trigger windows up to ≈3 µs at the maximum sampling rate. The platform enables sustained readout rates of up to 125 k events/s in zero-deadtime mode, enabled by the internal trigger logic.

## 2. Variable Adaptive Readout Capabilities

AARDVARC's adaptive architecture offers dynamic configurability for several critical parameters. The sampling rate is servo-controllable between 10 and 14 GSa/s via the DLL/PLL. Regions of interest are user-defined by specifying start and stop pointers within the 32 k sample buffer.

Per-channel discriminator thresholds can be programmed for optimized event selection. On-chip gain-adjust compensation via programmable front-end feedback resistors is included in the design (under development). Channel-by-channel clock phase skew is trimmable in 1 ps steps for optimal alignment.

The on-chip microcontroller autonomously executes calibration routines such as pedestal collection and linearity scans. Firmware in the on-board FPGA manages the trigger logic (AND/OR constructs between channels), timestamping, ROI windowing, and high-speed serialization of waveform data. Configuration registers are accessed by host software (NaluScope) over an SPI interface.

## 3. Performance Metrics and Experimental Validation

In electrical validation with calibrated input delay and double-exponential waveforms, the readout jitter ($\sigma_\text{readout}$) was measured as 79 ps (Gaussian width) in internal trigger mode and improved to 51 ps when using external trigger synchronization. For single-photoelectron (SPE) events in LAPPD + AARDVARC measurements, the inter-channel delay mean was −308 ps (−3.08 samples), with total system jitter $\sigma_\text{total} = 360$ ps. When compared to fast oscilloscope readout (25 GSa/s), the total time jitter was 105 ps, enabling decomposition of variance contributions from laser, LAPPD, and readout electronics using

$$
\sigma_\text{total}^2 = \sigma_\text{laser}^2 + \sigma_\text{LAPPD}^2 + \sigma_\text{readout}^2.
$$

This decomposition yields $\sigma_\text{LAPPD} \approx 100$ ps for the tested Gen 2 device. Input-referred noise for AARDVARC is approximately 1 mV RMS. Per-sample SNR is 74 dB (ideal 12-bit quantization), with effective SNR observed at 60 dB, primarily limited by the analog front-end. The analog bandwidth supports pulse rise-times with under 5 ps broadening.

## 4. Control, Calibration, and Firmware

AARDVARC integrates an embedded microcontroller for internal calibration tasks, including pedestal subtraction (periodic baseline capture below 1 Hz trigger rate), single-channel digitizer linearity ramps, and storage of calibration coefficients on-chip. On-die thermal sensors feed back to the DLL control voltage for temperature-driven timing stability.

The host FPGA fabric implements logic for multi-channel trigger formation, region-of-interest data reduction, and high-speed packetization. Configuration and slow control use an SPI-like protocol, while data transfer to host PCs is achieved through 1 Gb Ethernet, with custom event-packet headers encoding timestamps, channel masks, and ROI pointers.

## 5. Integration with Large Area Picosecond Photodetectors (LAPPDs)

AARDVARC is designed for direct interfacing with Gen 2 LAPPDs, which feature an 8×8 pad anode array. Each pad output is connected to the readout via SMA cables, passing through backplane transformers for 50 Ω matching and capacitive coupling. The LAPPD operates under high-voltage bias supplied through five independent SHV connectors. Synchronization for photo-detection is accomplished via a delay-generator providing a TTL sync to the chip and laser source.

Two operational trigger modes exist: internal (discriminator above threshold in any channel prompts ROI sampling) and external (external TTL triggers synchronized to optical events). FPGA timestamping and Ethernet streaming facilitate real-time acquisition, with visualization and control through the NaluScope GUI. NaluScope allows configuration of sampling parameters and provides live waveform display and data export for offline analysis in Python/ROOT.

## 6. Comparative Analysis and Physical Characteristics

The following table summarizes the comparative metrics of AARDVARC alongside the HDSoC platform:

| Parameter            | HDSoC             | AARDVARC           |
|----------------------|-------------------|--------------------|
| Channels             | 32/64             | 4/8                |
| Sampling rate (GSa/s)| 1–3               | 10–14              |
| Analog bandwidth     | 1 GHz             | >1.6 GHz           |
| Buffer depth         | 2048/ch.          | 32,768/ch.         |
| Trigger buffer       | ≈2 µs             | ≈3 µs              |
| Timing resolution    | <100 ps           | <5 ps (DLL spec)   |
| Max event rate       | 23 kHz/ch         | 125 kHz total      |
| Power per channel    | 20–40 mW          | 80 mW              |
| Process node         | 250 nm CMOS       | 130 nm CMOS        |
| ADC bits             | 12                | 12                 |

AARDVARC’s implementation in 130 nm CMOS occupies a die area of approximately 100 mm² and operates at a nominal core voltage of 1.2 V (0.3–0.9 V adjustable), with I/O at 3.3 V. Each channel draws roughly 80 mW, including front-end, SCA, and ADC power.

## 7. Application Prospects and Future Directions

AARDVARC’s combination of high analog bandwidth, deep buffering, per-channel configurability, and sub-100 ps timing supports low-flux Cherenkov and scintillation photon detection in large-scale neutrino detectors and related experiments. Its region-of-interest digitization, on-chip calibration, and scalable firmware facilitate detailed single-photoelectron studies and complex multi-channel coincidence analyses.

A plausible implication is that further scaling to higher channel counts, improved cross-talk characterization, and the implementation of on-chip constant fraction discriminator (CFD) timing would broaden usability in larger LAPPD arrays and next-generation timing-sensitive physics detectors [2511.22765]. Ongoing and future studies aim to quantify channel-to-channel cross-talk and optimize variant firmware for high-density deployments.

Source: https://www.emergentmind.com/topics/variable-adaptive-readout-chip-aardvarc