---
title: Ultra-Low-Power Analog Neuron
url: https://www.emergentmind.com/topics/ultra-low-power-analog-neuron
type: topic
---

# Ultra-Low-Power Analog Neuron

An ultra-low-power analog neuron is a circuit-level abstraction that emulates the essential biophysics of biological neurons while achieving multi-femtojoule (fJ) to sub-picojoule (pJ) energy-per-event. These neurons are implemented in advanced CMOS, FDSOI, or post-CMOS processes and are optimized for neuromorphic computing, edge sensory interfaces, event-driven ADCs, and memory-in-compute architectures. Design strategies exploit subthreshold operation, minimal active device counts, compact capacitive elements, and circuit innovations such as power-gating, dynamic adaptation, and event-driven resets to suppress static and dynamic energy dissipation while retaining flexible neural functionality. Exemplars include leaky integrate-and-fire (LIF) neurons in advanced nodes, analog-mixed-signal circuits, spintronic and ferroelectric hybrids, time-based integrate-and-fire, and level-crossing-based neuron-ADC front-ends.

## 1. Fundamental Circuit Principles and Energy Efficiency

Ultra-low-power analog neurons systematically minimize both static and dynamic energy through architectural simplicity and device-level exploitation of subthreshold MOSFET operation. The canonical LIF neuron is implemented as a small current mirror driving a capacitance of a few femtofarads, with energy per spike determined by the voltage swing $\Delta V$ and membrane capacitance $C_{\mathrm{mem}}$:
$$
E_{\mathrm{spike}} \approx C_{\mathrm{mem}}\, \Delta V^2
$$
The 28 nm TSMC neuron achieves $E_{\mathrm{spike}} = 1.61\,\mathrm{fJ}$ at $C_{\mathrm{mem}} \approx 3.47\,\mathrm{fF}$ and $\Delta V \sim 50\,\mathrm{mV}$. Currents are in the pA–nA range, and static leakage is suppressed by careful sizing, biasing, and occasionally by body-bias or power-gating [2408.07734].

Supply voltages as low as 250 mV ($V_{\mathrm{DD}}$) are supported in optimized topologies, enabled by low-threshold devices and careful noise margin budgeting. Device count is minimized (≤8 MOSFETs per neuron), and compact capacitors exploit advanced layout (MOM/fringe).

Energy per conversion or operation in specialized ADC or mixed-signal neural front-ends drops to sub-100 fJ/conversion at effective numbers of bits (ENOB) ≳6.5, as shown in level-crossing sampled architectures [2211.15319]. Mixed-signal MAC blocks realize energy per operation in the attojoule regime [1806.05141].

## 2. Topological and Architectural Variants

### 2.1 Subthreshold CMOS LIF Neuron

A basic LIF neuron is composed of a current-mirror integrator, subthreshold inverters as threshold comparators (spike generator), and a reset block. Subthreshold operation ensures exponential I–V characteristics:
$$
I_D = I_0\,e^{\frac{q(V_{GS}-V_{th})}{n\,k_BT}}
$$
Reset and refractory are implemented via coupling capacitors and additional switches, with spike times as fast as $f_{\text{max}} = 300\,\mathrm{kHz}$ demonstrated at $250\,\mathrm{mV}$ on 28 nm silicon [2408.07734], supporting high-speed SNNs.

### 2.2 Adapting for Level-Crossing and Reconfigurable ADC Functionality

The Neuron-ADC leverages a level-crossing sampler and bio-inspired refractory to achieve event-driven, data-compressing conversion. Critical components are:
- Two dynamic comparators (with 3-stage cascaded PMOS input differential amplifiers and tail-power-gating) determine “up” and “down” crossings.
- A refractory circuit based on a PMOS common-source stage and NMOS discharge load generates adjustable dead-times, tunable by $V_{\text{REF}}$.
- Digital logic for reset and folding.

The architecture enables dynamic selection between low-power/sparse operation and high-accuracy/dense conversion by modulating the refractory period:
$$
FoM = \frac{\text{Power}}{2 \cdot BW \cdot 2^{ENOB}}
$$
A figure-of-merit (FoM) of $97\,\mathrm{fJ/conversion}$ and up to $6.9$ ENOB is obtained at $0.6$ V [2211.15319]. Power-gating comparators reduce static comparator drain by up to $41.1\,\%$ at $10\,\mathrm{kHz}$.

### 2.3 Time-Domain and Phase-Based Neurons

Time-domain analog neurons eschew voltage-mode integration in favor of phase or timing-based summation and thresholding. Weighted-sum integration is transformed to a first-crossing output time, as in TACT (time analog computation) neurons, which have demonstrated $>290\,\mathrm{TOPS}/\mathrm{W}$ in macroscale simulation [1810.06819].

A representative circuit employs NMOS gating, current-controlled oscillators, and digital counters for “reset by subtraction,” guaranteeing high linearity (error $<1\%$), ultra-low power ($0.23\,\mu\mathrm{W}$ per neuron), and whole-network energy/inference below $3.72\,\mathrm{nJ}$ at $1\%$ error on MNIST [2202.02015].

## 3. Device and Process Innovations

### 3.1 Advanced SOI and FDSOI Techniques

Utilizing FDSOI (Fully Depleted SOI) technology, body-biasing allows dynamic adjustment of threshold voltages and leakage suppression. Self-cascoding in current mirrors stabilizes sub-pA currents, and large APMOM capacitors implement slow, biophysically-realistic time constants:
$$
\tau_{leak} = \frac{C_{\text{mem}}}{I_{\text{leak}}}
$$
Tunable by sweeping $I_\tau$ from $500\,\mathrm{fA}$ down to $1\,\mathrm{fA}$, time constants reach seconds, with energy per spike from $\sim 16\,\mathrm{pJ}$ at $30\,\mathrm{Hz}$ down to $\sim 1\,\mathrm{pJ}$ at $2\,\mathrm{kHz}$ [2006.14270].

### 3.2 Integration with Emerging Memory Devices

Hybrid ferroelectric tunnel junction (FTJ)-CMOS neurons realize the integrate-and-fire operation with capacitive elements of $1$–$10\,\mathrm{fF}$, see spike energies of $2$–$10\,\mathrm{fJ}$, and exhibit non-volatile membrane state retention, enabling duty-cycled operation and minimizing standby [2211.02598]. Electrical tuning is possible via coercive field and inverter threshold adjustments.

Memristive and spintronic domains—e.g., SOT-MRAM-based neurons or domain wall magnets—enable further reductions in energy/area, analog-friendly sigmoid/soft-limiting transfer, and direct crossbar integration. SOT-MRAM neurons achieve $72\,\mathrm{fJ}$ per activation, $0.138\,\mu\mathrm{m}^2$ area and are fully compatible with analog IMC macros [2204.09918].

## 4. Noise, Fidelity, and Operation Under Variability

Thermal and flicker noise, device mismatch, and PVT variations are central to the behavior and energy scaling of ultra-low-power analog neurons. Subthreshold MOSFETs introduce $\mathrm{fA}$-scale leakage and $1/f$ noise; design must ensure sufficient headroom for distinguishability of spike events. Monte-Carlo simulation of neuron firing rate variability at $70\,\mathrm{Hz}$ yields a CV of $13\%$ [2006.14270]. 

The intrinsic threshold for spiking may be quantified as an internal membrane potential $V_{\mathrm{th}}$ that is invariant to pulse shape; statistical analysis shows that deterministic thresholds bifurcate into distributions under strong noise, impacting spike-timing reliability and first-passage metrics [2511.12753].

Neural networks and SNNs are highly error-resilient: injected non-idealities up to $0.1\,\mu\mathrm{V}^2$ integrated noise or $±3\sigma$ of device mismatch affect MNIST/CIFAR10 accuracy by less than $2.1\%$ (worst-case) [1806.05141].

## 5. System Integration, Scalability, and Trade-Offs

Ultra-low-power analog neurons function as core primitives in:
- Neuromorphic edge SoCs and event-driven sensory front-ends [2408.07734]
- Bio-signal compressors (e.g., EEG, ECG) [2211.15319]
- Memory-in-compute platforms leveraging eNVMs and memristive crossbars [2305.16187, 2204.09918]
- Associative memories and non-Boolean computation using spin and ferroelectric physics [1304.2281, 2211.02598]

Trade-offs are central: 
- **Sampling vs. Power**: Shortened refractory improves accuracy and bandwidth at the cost of dynamic power; decreasing $V_{\mathrm{REF}}$ yields fewer, lower-power events.
- **Membrane Capacitance vs. Fan-In**: Larger $C_m$ supports greater fan-in but at the expense of slower operation and increased area.
- **Supply Voltage**: Lowering $V_{\mathrm{DD}}$ quadratically reduces $E_{\mathrm{spike}}$, but at the risk of noise margin collapse; threshold-tuned devices, body bias, and tailored device flavors (FDSOI) are needed.

Tabulated summary of recent ultra-low-power analog neuron metrics:

| Work                     | Node      | $E_{\mathrm{spike}}$   | Area ($\mu m^2$) | Max $f$      |
|--------------------------|-----------|------------------------|------------------|--------------|
| [2408.07734]             | 28 nm     | 1.61 fJ                | 34               | 300 kHz      |
| [2211.15319] (ADC)       | 40 nm     | 97 fJ/conversion       | N/A              | $>10$ kHz    |
| [1810.06819] (TACT)      | 250 nm    | $\sim$6.9 fJ/op        | PoC              | $>290$ TOPS/W|
| [2204.09918] (MRAM)      | 14 nm     | 72 fJ                  | 0.138            | 250 MHz      |
| [2006.14270] (FDSOI)     | 22 nm     | 1–16 pJ                | $\sim$1000       | 2 kHz        |

## 6. Application Domains and Outlook

Ultra-low-power analog neurons are foundational for event-based signal encoding, biomedical interfaces, edge inference, analog-to-digital front-ends, and co-located memory-compute platforms. Demonstrated integration in SNNs with surrogate gradient training yields competitive accuracy (e.g., 82.5% on MNIST post 4-bit quantization in [2408.07734]), validating their applicability.

Future directions include integration with eNVM synapses, advanced 3D die stacking, photonic or multi-physics hybrid neuron implementations, and sub-100 mV supply operation. Further advances in device matching, noise mitigation, crosstalk suppression, and dynamic adaptation will enable even lower energy budgets and increased scalability for emerging neuromorphic processors.

Source: https://www.emergentmind.com/topics/ultra-low-power-analog-neuron