---
title: Silicon Two-Qubit Logic Gate
url: https://www.emergentmind.com/topics/two-qubit-logic-gate-in-silicon
type: topic
---

# Silicon Two-Qubit Logic Gate

A two qubit logic gate in silicon is a fundamental operation that enables the creation of entanglement, conditional gates such as CZ, CNOT, or SWAP, and ultimately forms the basis for universal quantum computation on scalable, nanofabrication-compatible platforms. In silicon systems, two-qubit gates have been realized using a range of modalities—electrically gated singlet-triplet exchange, spin–photon coupling, resonant driving, shuttling-mediated exchange, encoded subspace logic, and hybrid photonic approaches—spanning a diverse set of architectures and physical encodings.

## 1. Device Architectures and Physical Qubit Realizations

Silicon two-qubit gates have been demonstrated in several physical implementations:

- **Gate-defined quantum dots:** Single or double quantum dot (DQD) devices with electrons or (increasingly) holes in Si/SiGe or MOS heterostructures are the dominant platform. Two-qubit gates utilize nearest-neighbor exchange between single-spin qubits manipulated with either ESR or EDSR, with tunable tunnel couplings (e.g., [1411.5760], [2108.02626], [1910.05289], [2007.09034]).
- **Donor-based qubits:** Heisenberg-coupled ^31P donor electrons/ions in ^28Si enable atomic-scale precision with demonstrated conditional-rotation (CROT) gates, robust even with weak or static exchange interaction ([2006.04483], [2309.15463]).
- **Mobile electron spin qubits:** Phase-coherent electron shuttling (“conveyor-mode”) extends two-qubit logic to dynamically configurable dot arrays and offers non-local entanglement, as demonstrated both for stationary shuttle between adjacent dots [2202.01357] and for two mobile carriers meeting in a sparse channel [2503.15434].
- **Resonator-mediated gates:** Superconducting microwave resonators enable long-range (250 μm) coherent coupling between DQDs via virtual photons and achieve fast iSWAP gates ([2310.16805]).
- **Hole-spin FinFETs:** Strong spin–orbit interaction in Si FinFETs leads to anisotropic exchange, supporting ultrafast conditional-rotation with high theoretical fidelity and reduced charge/noise sensitivity ([2212.02308], [2508.00446]).
- **Encoded spin qubits:** Logic in decoherence-free subsystems, e.g., 3-spin exchange-only “DF subsystem” in six-dot SLEDGE arrays, uses only nearest-neighbor baseband pulses ([2202.03605]).
- **Silicon photonics:** Linear-optic architectures on an SOI platform implement controlled-Z gates for dual-rail photonic qubits, leveraging path encoding and postselection ([1709.00214]).

Table 1 provides a non-exhaustive comparison of typical parameters across representative silicon two-qubit gate experiments.

| Platform            | Gate type     | Gate time (ns) | Gate fidelity (%) | Key Challenges          |
|---------------------|--------------|----------------|-------------------|-------------------------|
| Exchange, DQD       | CZ/CROT      | 60–700         | 91–99.5           | Charge noise, dephasing |
| Donor-based         | CROT         | 50–200         | >99.9 (projected) | Precise donor position  |
| Conveyor-mode       | CZ           | 58             | 98.9              | Shuttle stability       |
| Resonator-mediated  | iSWAP        | 10–40          | 67–83             | Hybridization, loss     |
| Anisotropic (holes) | CROT         | 24–100         | up to 99.7 (Q est)| SOI engineering         |
| Encoded (DFS)       | CNOT/SWAP    | 20–45×pulse    | 93.8–99.3         | Pulse complexity        |
| Photonic            | CZ (postsel) | —              | 83–97 (state F)   | Loss, postselection     |

## 2. Underlying Hamiltonians and Gate Mechanisms

The canonical two-qubit interaction in silicon is the Heisenberg exchange, realized either via direct overlap of spin wavefunctions or through virtual excitations in a mediator (e.g., a superconducting resonator). The generic two-qubit Hamiltonian takes the form:
\[
H(t) = J(t)\,\mathbf{S}_1 \cdot \mathbf{S}_2 + \sum_{i=1,2} g\mu_B B_i S_{z,i},
\]
where $J(t)$ is tuned rapidly by barrier or detuning pulses, and $B_i$ includes external and engineered field gradients (micromagnets, hyperfine fields).

- **Native CZ gates:** By pulsing $J(t)$ on for time $\tau$, a conditional phase $\phi = \int_0^\tau J(t)\,dt/\hbar$ is accumulated between $|\uparrow\downarrow\rangle$ and $|\downarrow\uparrow\rangle$. Setting $\phi = \pi$ (up to single-qubit $Z$ rotations) realizes a CZ gate. Decoupled CZ (“DCZ”) sequences, with echo $\pi$-pulses on both qubits, suppress low-frequency noise ([2202.01357], [2409.09747], [2508.00446]).

- **CROT/CNOT gates:** With finite exchange, the target qubit’s transition frequency splits depending on the control’s spin. Selective driving at the conditional frequency implements a conditional-rotation (CROT), operationally equivalent to CNOT up to basis choice ([2108.02626], [1910.05289], [2212.02308], [2006.04483]).

- **SWAP/iSWAP gates:** In regimes with $J\gg\Delta E_z$, the exchange oscillates |↑↓⟩ and |↓↑⟩ at frequency $J$, effecting a full SWAP or $\sqrt{\mathrm{SWAP}}$ in times governed by $t = \pi/J$ or $t = \pi/(2J)$, respectively ([2310.06700], [2409.00601]).

- **Encoded/DFS logic:** For 3-spin encodings, Clifford and entangling gates are decomposed into sequences of selective exchange pulses, exploiting pulse symmetries and decoherence-free subspaces ([2202.03605]).

- **Long-range gates:** Resonator-mediated coupling projects to an effective $H_\mathrm{eff} = \hbar J (\sigma_{1}^+\sigma_{2}^- + \sigma_{1}^- \sigma_{2}^+)$, yielding iSWAP dynamics. The coupling rate $J$ is set by spin–photon coupling $g_s$ and detuning $\Delta$ ([2310.16805]).

- **Anisotropic exchange in holes:** The spin–orbit interaction causes the exchange tensor to be highly anisotropic; with $J_\perp \ll J_\parallel$, highly selective CROT gates are attainable without speed–fidelity trade-off ([2212.02308]).

## 3. Gate Pulse Engineering and Calibration Protocols

Practical two-qubit gate operation relies on precise electrical pulsing, noise-resilient sequences, and real-time calibration.

- **Pulse shaping:** Sub-nanosecond barrier/plunger pulses control tunnel couplings, adiabatic or diabatic exchange, and shuttle timings ([2202.01357], [2503.15434], [2409.09747]). Square, Gaussian, or optimized composite pulses are used to balance speed, spectral selectivity, and robustness ([2007.09034]).
- **Phase correction:** Accrued single-qubit phases during exchange are either measured and corrected virtually (by phase shifts in the control frame), or automatically refocused in DCZ/echo sequences ([2310.06700], [2409.09747]).
- **Real-time feedback:** Automated calibration of qubit Larmor frequencies, exchange amplitudes, and microwave phases is realized via FPGA-based feedback piping, with update rates $\sim0.6$ s per channel ([2309.12541]).
- **Noise monitoring:** Continuous wavelet transforms and real-time post-processing enable identification of slow drifts, discrete telegraph noise, and band-limited $1/f$ fluctuations, supporting adaptive error mitigation.

## 4. Performance Benchmarks and Error Sources

Fidelity assessment employs randomized benchmarking (RB), gate set tomography (GST), Bell-state tomography, and Q-factors.

- **Randomized benchmarking:** Clifford and interleaved RB yield two-qubit gate fidelities up to 99.5% ([2108.02626]), with single-qubit gates routinely >99.8%. Native CZ, CNOT, CROT, and SWAP fidelities in the best experiments are in the 96–99.7% range ([2202.01357], [2503.15434], [2310.06700], [2508.00446]).
- **Error budget:** Dominant errors arise from charge noise coupling to the exchange (via $\partial J/\partial V$), low-frequency nuclear Overhauser noise, and slow drifts (ΔE_z, $T_2^*$, residual J). Thermal effects, calibration drifts, and drive crosstalk are mitigated but not eliminated.
- **Coherence:** Echoed $T_2$ up to 28 μs is observed with isotopically purified $^{28}$Si ([2202.01357]), and $T_2^*$ up to 100 μs at the single-spin level ([1411.5760]). Bell-state preparation achieves fidelities in the 84–98% regime depending on SPAM correction and noise ([2107.14473], [2309.15463], [2409.09747]).

## 5. Scalability and Architectures for Large-Scale Processors

Silicon two-qubit logic is designed for modular, extensible architectures:

- **Nearest-neighbor arrays:** Direct exchange is suited to planar arrays, with virtual-gate “symmetrization” and automated tuning scaling to >6-dot, >500-dot buses ([2202.01357], [2202.03605]).
- **Dynamic connectivity:** Shuttling- and conveyor-mode architectures allow reconfigurable quantum bus topologies and non-local gates, supporting error correction layouts with flexible code geometry ([2503.15434]).
- **Long-range links:** Superconducting resonator coupling permits “all-to-all” logic over mm-scale separation, mitigating wiring bottlenecks ([2310.16805]).
- **CMOS integration:** FinFET-based hole devices, single-layer SLEDGE arrays, and standard MOS process flows enable monolithic integration of two-qubit logic with classical control ([2212.02308], [2508.00446], [2202.03605]).
- **Thermal robustness:** Operation at $T>1$ K via large valley/spin-blockade splitting allows co-integration with classical CMOS circuitry, overcoming cooling power limitations ([1910.05289], [2007.09034]).
- **Device yield:** High-fidelity, repeatable two-qubit gates have been demonstrated across multiple foundry-compatible platforms, including 300 mm processed MOS chips ([2508.00446]).

## 6. Advanced Gate Designs: Geometric and Encoded Approaches

To enhance robustness to slow noise and enable fault-tolerant thresholds:

- **Geometric gates:** Suitable pulse engineering in the large-gradient regime (ΔB_z ≫ J) supports geometric CZ and iSWAP gates with calculated fidelities >99.9%, outperforming purely dynamical gates under similar noise ([2409.00601]).
- **Encoded logic:** Exchange-only encoded qubits in decoherence-free subspaces (three-spin codes) achieve CNOT and SWAP gates natively in the computational group via pulse symmetries, achieving >97% Clifford fidelity ([2202.03605]).

## 7. Outlook and Challenges

Key open challenges include engineering robust coupling over tens to hundreds of microns, minimizing cross-talk in dense arrays, stabilizing against slow charge drifts, mitigating Overhauser noise, and integrating fast, nondestructive readout compatible with classical control tiers.

The diverse set of two-qubit logic gates now demonstrated in silicon (CZ, CNOT/CROT, SWAP/iSWAP, encoded gates, geometric gates, and photonic CZ in SOI) together set the foundation for large-scale, fault-tolerant silicon quantum computing architectures [2202.01357, 2310.16805, 2503.15434, 1910.05289, 2310.06700, 2212.02308, 2309.15463, 2006.04483, 2409.09747, 1411.5760, 2107.14473, 2309.12541, 2409.00601, 1808.08659, 2202.03605, 2007.09034, 2108.02626, 2508.00446, 1709.00214].

Source: https://www.emergentmind.com/topics/two-qubit-logic-gate-in-silicon