---
title: 'Tianyan-287: 105-Qubit Superconducting Quantum System'
url: https://www.emergentmind.com/topics/tianyan-287
type: topic
---

# Tianyan-287: 105-Qubit Superconducting Quantum System

Tianyan-287 is a cloud-accessible **105-qubit superconducting quantum computing system** on the **Tianyan Quantum Cloud Platform**, built around a **“\(Zuchongzhi\ 3.0\)-like” superconducting quantum processor** and presented as a service capable of **quantum advantage** on a flagship **74-qubit random circuit sampling (RCS)** benchmark. In the reported configuration, the platform provides access through the open-source **Cqlib** SDK, and the principal performance claims are **99.90%** single-qubit gate fidelity, **99.56%** two-qubit gate fidelity, and **98.7%** readout fidelity, together with a benchmark result of **one million samples in 18.4 minutes** for a **74-qubit, 24-cycle** circuit [2512.10504].

## 1. System identity and platform role

Tianyan-287 is described as the flagship cloud-accessible superconducting system in the paper **“Tianyan: Cloud services with quantum advantage”** [2512.10504]. It belongs to the broader **Tianyan Quantum Cloud Platform**, which is presented as a multi-system service including **Tianyan-287, Tianyan-176, Tianyan-504, and Tianyan-24**. The paper repeatedly characterizes Tianyan-287 as being **“equipped with a \(Zuchongzhi\ 3.0\)-like superconducting quantum processor”** or a **“\(Zuchongzhi\)-3.0-like quantum processor.”** The supported wording is therefore that Tianyan-287 is **Zuchongzhi 3.0-like**, not that it is literally the original Zuchongzhi 3.0 chip.

The platform is framed as more than a one-off benchmark vehicle. It is described as a **cloud service for high-performance quantum hardware**, as a mechanism for **democratizing access** to leading superconducting processors, and as a means for the community to **validate and explore practical quantum advantage**. The conclusion further characterizes it as **“the first commercial cloud-access to leading quantum computing power”** [2512.10504].

A key distinction in the paper is between the broad service claim and the direct experimental evidence. The direct evidence is a **74-qubit random circuit sampling** experiment with a runtime comparison against classical **tensor network simulation** estimates. This suggests that Tianyan-287 is positioned simultaneously as a hardware platform, a cloud service, and a public-facing benchmark system.

## 2. Processor architecture and operating characteristics

Tianyan-287 is a **superconducting quantum processor** with **105 qubits** and **182 couplers** in a **square grid lattice** [2512.10504]. The paper distinguishes between physical, working, and benchmarked qubit counts. The headline device size is **105 physical qubits**; Appendix A reports **104 working qubits**, because **one qubit is non-functional**; and the flagship RCS experiment uses a selected **74-qubit subset** rather than the full processor. The paper does not describe all 105 qubits as participating in the flagship benchmark.

The architectural description in the text is limited but specific. The processor uses **frequency tunability**, **iSWAP-like two-qubit gates**, and a square-grid connectivity pattern. The terminology of tunable frequencies, DRAG calibration, anharmonic-level readout involving the \(0\rightarrow2\) transition, and tunable couplers strongly indicates a transmon-style superconducting architecture, but the paper does not explicitly name the qubit type. The most precise supported description is therefore **superconducting qubits with 182 couplers in a square grid lattice**.

The reported coherence figures separate whole-device averages from the tuned benchmark subset. In the main text, the whole Tianyan-287 system is reported to have mean operating values of **\(T_1 = 44.4~\mu\text{s}\)** and **\(T_2^{CPMG} = 41.1~\mu\text{s}\)**. Appendix A reports **\(T_1 = 45.2~\mu\text{s}\)** on the remaining **104 qubits** over a **500 MHz frequency tunable range**, which appears consistent with the main-text figure up to rounding or operating-point differences. For the tuned **74-qubit** RCS subset, after frequency selection and tuning, the reported averages are **\(T_1 = 47.7~\mu\text{s}\)** and **\(T_2^{CPMG} = 44.1~\mu\text{s}\)** [2512.10504].

The following summary organizes the hardware quantities explicitly reported in the paper:

| Quantity | Reported value | Context |
|---|---:|---|
| Physical qubits | 105 | Headline processor size |
| Working qubits | 104 | Appendix A; one qubit non-functional |
| Qubits in flagship benchmark | 74 | Selected calibrated subset |
| Couplers | 182 | Square grid lattice |
| Mean operating \(T_1\) | \(44.4~\mu\text{s}\) | Whole system, main text |
| Mean \(T_2^{CPMG}\) | \(41.1~\mu\text{s}\) | Whole system, main text |
| Tuned-subset \(T_1\) | \(47.7~\mu\text{s}\) | 74-qubit RCS subset |
| Tuned-subset \(T_2^{CPMG}\) | \(44.1~\mu\text{s}\) | 74-qubit RCS subset |

The paper also emphasizes **30-day stability monitoring** from **August 29 to September 28, 2025**, tracking daily averages of **\(e_1\)**, **\(e_2\)**, and **\(e_3\)**, defined respectively as single-qubit Pauli error, two-qubit Pauli error, and readout error. The text states that the observed long-term stability and uncertainty bands support **consistent system performance**, although it does not give explicit drift coefficients or day-to-day standard deviations [2512.10504].

By contrast, many low-level implementation details are not disclosed. The paper does **not** provide explicit information on refrigerator temperature, control electronics, multiplexing factors, cryogenic amplifiers, feedline arrangement, exact coupler topology, or per-qubit coherence tables. This omission is significant for reproducibility but does not alter the processor-level characterization.

## 3. Native operations, calibration, and reported fidelities

The native circuit ingredients described for Tianyan-287 comprise **single-qubit gates** randomly chosen from
\[
\{\sqrt{X}, \sqrt{Y}, \sqrt{W}\},
\]
**two-qubit iSWAP-like gates** arranged in patterns **A, B, C, D**, and readout operations using an **X12-gate-driven \(0\)-\(2\) readout method** [2512.10504]. Cqlib examples further mention optimization of the **“fsim” gate model**, indicating that the compiled two-qubit representation is handled in an fsim-like parameterized family during optimization, although the paper does not spell out a full native gate algebra.

The headline fidelities are stated both in the abstract and introduction: **99.90%** for single-qubit gates, **99.56%** for two-qubit gates, and **98.7%** for readout. The associated average error rates are given as
\[
e_1 = 1\text{\textperthousand} = 0.001,
\]
\[
e_2 = 4.4\text{\textperthousand} = 0.0044,
\]
and
\[
e_3 = 1.3\%.
\]
These averages are described for simultaneous full-system operation and are also reflected in the 74-qubit RCS region [2512.10504].

The calibration methodology is one of the clearer methodological parts of the paper. For **single-qubit gates**, the reported procedure uses an **optimal-control-theory-based scheme**, with **26 ns** gate time and joint optimization of **drive frequency**, **drive amplitude**, and **DRAG coefficient**. Crosstalk reduction includes an **anti-phase compensation cancellation technique**, and verification uses **fully-parallel cross-entropy benchmarking (XEB)**, yielding the reported **99.9%** average single-qubit fidelity.

For **readout**, the paper uses **X12-gate-driven 0-2 readout**, intended to reduce decoherence errors during measurement, together with a **synchronous state preparation and measurement protocol** to control correlated readout errors. The text states that correlated readout errors were controlled **below 2%**, with average readout error **\(e_3 = 1.3\%\)**, corresponding to **98.7%** readout fidelity.

For **two-qubit iSWAP-like gates**, the gate length is fixed at **40 ns**. The optimal swap frequency is obtained by parameter scanning, and fine calibration based on **odd-numbered gate sequences** adjusts **coupling strength \(g\)** and **detuning frequency**. To improve large-scale operation, the paper reports a **dual compensation mechanism**, **dynamic coupling-off technology** to reduce residual adjacent-coupler interaction, and **idle gate benchmarking and calibration** to improve stability. XEB is used for verification across all **A/B/C/D** patterns on the 74-qubit system [2512.10504].

The paper is explicit about what it does **not** report. It does not provide randomized benchmarking formulas, simultaneous RB decay fits, explicit XEB equations, Porter-Thomas statistics, heavy-output probability formulas, or full per-qubit and per-edge numerical tables. It repeatedly invokes **XEB** and estimated fidelity from an **XEB model**, but the equations themselves are not printed in the supplied text. A plausible implication is that the paper prioritizes system-level performance demonstration and service deployment over low-level methodological completeness.

## 4. Random circuit sampling and the quantum-advantage claim

The flagship benchmark is a **random circuit sampling** experiment on a **74-qubit subset** of Tianyan-287, with circuits up to **24 cycles** [2512.10504]. The 74-qubit subset is a selected region of the larger processor rather than an arbitrary truncation: one qubit is non-functional, unused qubits are parked at **minimum operating frequency**, unused couplings are **deactivated**, and the benchmarked region is chosen for stable coherence and calibrated couplers. The paper therefore presents the benchmark as operating on a carefully selected high-quality subgraph, not on all **105** physical qubits.

Each cycle uses random single-qubit gates from
\[
\{\sqrt{X},\sqrt{Y},\sqrt{W}\}
\]
and iSWAP-like two-qubit gates in predefined patterns **A, B, C, D**. The main text states that these are arranged in the sequence **ABCD–CDAB** within each cycle, while the Figure 2(b) caption gives **ABCDCDBA**. This is an internal inconsistency in the paper, and the text does not reconcile it.

The benchmark’s headline runtime claim is that Tianyan-287 generated **1,000,000 samples** in **18.4 minutes**. For the largest full **74-qubit, 24-cycle** configuration, the main text reports approximately
\[
9.13 \times 10^7
\]
bitstrings, while the figure caption states
\[
91.255 \text{ million bitstrings}.
\]
These values are effectively consistent up to rounding [2512.10504].

Because the ideal output distribution of the full 74-qubit circuit is classically hard to compute, the paper adopts a **patch-circuit** validation strategy. It constructs a **four-patch version** of the circuit by selectively removing inter-region two-qubit gates, and then compares this with the full circuit over **8–24 layers**. The stated rationale is that the patch circuits remain verifiable while retaining enough structure to calibrate a **discrete error model**, which then predicts full-circuit fidelity.

The reported benchmark fidelities are numerically small but central to the claim. For the **74-qubit four-patch circuit** at the largest configuration, the paper gives **experimental fidelity: 0.056%** and **estimated fidelity: 0.064%**. For the **full 74-qubit 24-cycle circuit**, the **estimated fidelity** is **0.054%** [2512.10504]. The paper interprets these values as sufficient to place the sampling task in a nontrivial regime beyond practical classical simulation.

The classical comparison is based on **tensor network simulation** under two scenarios. In the **Frontier-memory-constrained case**, with memory limit **9.2 PB**, the paper estimates that generating **1 million independent bitstrings** at **0.054% fidelity** requires
\[
2.1 \times 10^{28}
\]
FLOPs. Using Frontier’s theoretical peak of
\[
1.685 \times 10^{18}
\]
single-precision FLOPs/s, together with assumptions of **20% floating-point efficiency** and **8 machine FLOPs** per single-precision complex FLOP, the runtime estimate becomes
\[
1.6 \times 10^{4}\ \text{years}.
\]
In a second, nearly unlimited-memory lower-bound scenario, with over **762.2 PB** including total memory and storage, the required work is
\[
1.8 \times 10^{25}
\]
FLOPs, corresponding to **19 years**. The paper emphasizes that this lower bound is not practically feasible because the memory assumption is unrealistic [2512.10504].

This benchmark is the foundation of the quantum-advantage claim. At the same time, the paper explicitly notes that **“RCS tasks based on iSWAP-like gates have limited practical application.”** The significance is therefore framed as proof that the hardware-and-service stack can sustain large-scale cloud execution, rather than as a direct application speedup for a useful end-user problem.

## 5. Cloud software stack and service workflow

Tianyan-287 is exposed to users through a cloud workflow centered on **Cqlib**, the platform’s open-source SDK [2512.10504]. The paper describes Cqlib as supporting quantum work at the level of **extended circuits**, **operators**, and **primitives**. Appendix A adds that it is built on **QCIS (Quantum Computing Instruction Set)** and provides end-to-end support for **circuit construction**, **compilation**, **optimization**, **simulation**, **visualization**, and **result output**.

The workflow described in the paper has four stages: **circuit construction**, **transpilation**, **execution**, and **post-processing**. The stated cloud-service model is that circuits are constructed locally in Cqlib, transpiled for a chosen target machine, submitted to the Tianyan backend, and later retrieved with execution results. The scheduling system manages **task queuing** and distribution across **heterogeneous resources**, including **quantum hardware systems, quantum circuit simulators, and HPC servers**. The paper explicitly characterizes the **HPC servers** as a **classical collaborator**, coordinating circuit dispatch, sample collection, and data processing, with local compact deployment enabling **low-latency hybrid iteration**.

The paper includes concrete API-level examples. Circuit construction uses `cqlib_experiments.rcs.circuit.setup_circuit_with_depth`, where users specify the logical qubit list, pattern connectivity for **A/B/C/D**, circuit depths, and number of random instances. Transpilation uses `TianYanPlatform`, `download_config(machine='tianyan-287')`, and `transpile(circuit, config)`. Execution uses `run_task(config, transpiled_circuits, shots=samples, auto_opt=True)` and `supremacy_result(task_id)`, with `auto_opt=True` triggering automatic optimization of the **fsim gate model** after sampling. Post-processing includes `download_data(task_id, file_name=...)` and `show_opt_parameters(config, task_id)` for retrieval of raw data, metadata, and optimization logs [2512.10504].

The software layer is also presented as an interoperability layer. The paper claims compatibility with **Tianyan** cloud hardware, **QuantumCTek** cloud hardware, and adapters to **Qiskit**, **Cirq**, and **PennyLane**. At the user-facing level, the paper mentions a **login key/API key** but does not disclose pricing, quotas, queue-time SLAs, reservation models, job-priority policies, concurrency limits, or formal public resource ceilings.

A practical statement appears in the service description: Tianyan can execute circuits with **more than 100 qubits** and **over 2000 gates**. However, the text does not provide a formal public limit table for maximum shots, wall-clock runtime, or memory. This suggests that the service is presented as operationally substantial, but not fully documented in the manner of a cloud systems specification.

## 6. Scope, limitations, and disambiguation

The paper is explicit that Tianyan-287’s flagship result is a **quantum advantage on random circuit sampling**, not a demonstration of application-level acceleration on a useful workload [2512.10504]. It points to intended support for **scientific experiments**, **software development**, **hybrid quantum-classical tasks**, exploration of **near-term NISQ applications**, and eventually **fault-tolerant quantum computing**. It also notes prior Tianyan-system use in **quantum simulation**, **optimization**, and **machine learning**, and states that the team is developing **quantum machine learning libraries** and **quantum algorithm libraries**.

The reported limitations are substantial. First, **noise remains substantial**: the full-circuit RCS fidelity is only about **0.054%**. Second, the headline result uses **74 qubits**, not all **105**, and Appendix A separately notes **104 working qubits** because one qubit is non-functional. Third, the benchmark depends on extensive tuning, including **idle-frequency optimization**, **real-time \(T_1\) monitoring**, **dynamic re-tuning**, and compensation for **crosstalk** and **residual coupling**. Fourth, the benchmark itself is acknowledged to have **limited practical application**. Fifth, scalability details remain sparse: the paper does not quantify how calibration cost, drift management, or throughput scale with larger workloads.

The paper’s comparison to earlier work places Tianyan-287 in the lineage of **Google Sycamore-style random circuit sampling** and **USTC Zuchongzhi-style superconducting processors**. It cites **Willow** with **103 qubits, depth 40** and **Zuchongzhi 3.0** with **83 qubits, depth 32** as relevant precedents, while presenting Tianyan-287 as newer than **Tianyan-176 / Tianyan-176 II**, which used **Zuchongzhi 2.0-like** processors [2512.10504]. The paper’s novelty claim is therefore not only processor scale but also **commercial cloud accessibility to quantum-advantage-level hardware**.

A recurring potential misconception concerns the name **“287.”** In the astrophysical literature, **OJ 287** is a well-known blazar or quasar interpreted in some papers as a relativistically precessing binary black hole system [1112.1162; 1212.5206]. **Tianyan-287** is unrelated to that object. The overlap is purely nominal. This distinction matters because searches for “287” in arXiv and adjacent literatures can surface both the quantum-computing platform and the astrophysical source.

Taken together, the paper presents Tianyan-287 as a **cloud-accessible 105-qubit superconducting system** whose strongest direct evidence is a **74-qubit, 24-cycle random circuit sampling** experiment completed in **18.4 minutes** and compared against a classical estimate of approximately **\(1.6\times 10^4\) years** under stated tensor-network assumptions [2512.10504]. A plausible implication is that its historical significance lies less in a single benchmark number than in the attempt to turn quantum-advantage-class superconducting hardware into a remotely accessible cloud service with an exposed software workflow and repeatable operational envelope.

Source: https://www.emergentmind.com/topics/tianyan-287