---
title: Threshold-Programmable FETs
url: https://www.emergentmind.com/topics/threshold-programmable-fets
type: topic
---

# Threshold-Programmable FETs

Threshold-programmable field-effect transistors (FETs) are a class of devices in which the channel threshold voltage ($V_{th}$) can be precisely adjusted post-fabrication—either permanently or reversibly—via physical, chemical, or electrical means. This capability enables dynamic or in-field configurability of logic, memory, analog, and security primitives, extending the traditional role of the FET beyond static, process-defined characteristics. Techniques for threshold programming span from channel doping and work-function engineering to ferroelectric polarization control, fluidic or charge-based field effects, and active body biasing. Ongoing developments establish threshold programmability as fundamental in low-power logic, secure hardware, non-volatile memory, and neuromorphic systems.

## 1. Physical Mechanisms and Device Architectures

Multiple physical mechanisms underlie threshold-programmable FETs, each dictating device geometry, programming resolution, volatility, and application domain.

### 1.1. Doping and Work-Function Engineering  
Classic "threshold voltage-defined (TVD)" FETs leverage engineered channel doping and metal gate work-function selection to assign high- or low-$V_{th}$ states. HVT/LVT devices are realized via implant masks or localized work-function adjustment. Once set during front-end-of-line processing, these thresholds are permanent [1512.01581].

### 1.2. Ferroelectric Polarization Control  
Ferroelectric-gate FETs (FeFETs) employ polarization switching in a ferroelectric layer (e.g., Hf$_{0.5}$Zr$_{0.5}$O$_2$ or Al$_{0.68}$Sc$_{0.32}$N) to dynamically shift $V_{th}$ after fabrication. Each polarization state induces a remanent charge at the interface, modulating the channel electrostatics [2004.03903, 2411.03198]. The effect is robust and non-volatile, enabling multi-level or binary operation.

### 1.3. Electrochemical and Fluidic Modulation  
Ion-sensitive FETs (ISFETs) utilize changes in the ionic environment at the gate dielectric to affect surface potential, and consequently $V_{th}$, providing field/configuration reprogrammability without altering the solid-state device [2304.05686].

### 1.4. Field and Charge-Induced Programming  
Charge-trapping in dielectric stacks, as exploited in electron-beam programmable 2D FETs (e.g., WSe$_2$ on hBN/Al$_2$O$_3$), enables rewritable and site-selective $V_{th}$ tuning via external stimulus, with patterning at sub-micrometer resolution [2512.06318].

### 1.5. Dual-Gate and Body Bias  
Flexible-FETs and body-biasing architectures (e.g., DTMOS/VTMOS) actively modulate the channel potential barrier via a back-gate, substrate bias, or dynamic connection schemes, imparting electrical control over $V_{th}$ at runtime [1211.4564, 1003.6030].

**Programming Paradigms Table**

| Mechanism                | Modality      | Volatility / Endurance     |
|--------------------------|--------------|----------------------------|
| Channel doping/work-func.| One-time     | Permanent                  |
| Ferroelectric switching  | Multi-level  | Non-volatile, $10^6$ cycles|
| ISFET ion exchange       | Reversible   | Quasi-volatile, $\sim$10 h retention |
| Charge trapping (e-beam) | Rewritable   | Reversible, $>10$ cycles   |
| Body bias / Flexible-FET | Dynamic      | Volatile (active only)     |

## 2. Analytical Models and Threshold Shift Equations

Threshold programming requires rigorous control and predictability of $V_{th}$ modulation. Key mathematical formalisms relate the device parameters, structural features, and external stimuli to the resultant $V_{th}$.

### 2.1. Doping/Work-Function Based $V_{th}$  
In bulk MOSFETs:
\[
V_{th} = \Phi_{MS} - 2\phi_F - \frac{Q_{ox}}{C_{ox}} + \gamma \sqrt{2\phi_F + V_{SB}}
\]
where $\Phi_{MS}$ is the gate-to-channel work-function difference, $\gamma$ is the body-effect coefficient, and $V_{SB}$ is the source–body bias. HVT/LVT flavors differ by $\Delta V_{th} \approx \pm 0.35$–$0.4$ V [1512.01581].

### 2.2. Ferroelectric/Gate Polarization  
For FeFETs, the threshold shift due to polarization $P$:
\[
\Delta V_{th} = -\frac{P}{C_{ox}}
\]
or, for a multi-stack:
\[
\Delta V_{th} = -P \left(\frac{1}{C_{FE}} + \frac{1}{C_{ox}}\right)
\]
where $C_{ox}$, $C_{FE}$ are (ferro)electric capacitances per unit area [2004.03903, 2411.03198].

### 2.3. Electrochemical/ISFET  
ISFET $V_{th}$ includes a pH-dependent surface potential:
\[
V_{th}^{\mathrm{ISFET}} = V_{th0} - 2.3\frac{kT}{q} \alpha\ (\mathrm{pH} - \mathrm{pH}_{pzc})
\]
with ideal Nernstian response yielding $\sim$59 mV/pH at 25°C [2304.05686].

### 2.4. Charge-Trapping (e-beam)  
Modulated threshold in charge-trap FETs:
\[
\Delta V_{th} = \frac{Q_{dop}}{C_{ox}} + \phi_{ms}
\]
with $Q_{dop}=e\,\Delta n_{2D}$ directly controlled by patterning [2512.06318].

### 2.5. Flexible-FET Dual Gate  
Closed-form $V_{th}$ in Flexible-FETs:
\[
V_{th,top}(V_{g,bot}) = \Phi_{MS} + 2\phi_F + \frac{qN_{ch}t_{si}^2}{8\varepsilon_{si}} + \frac{C_{si}}{C_{ox}}(V_{g,bot} - V_{bi})
\]
[1211.4564].

## 3. Device Fabrication, Programming Workflows, and Performance Metrics

### 3.1. Fabrication Flow  
- **Doping/work-function:** Defined at mask/litho level, no post-process adjust.
- **Ferroelectric:** Integration of a 10–45 nm ferroelectric layer by ALD or PVD, annealed for crystallinity, with pulse-based programming post-fab [2004.03903, 2411.03198].
- **ISFET:** Standard CMOS flow, finished with Si$_3$N$_4$/Al$_2$O$_3$ passivation; gate set post-fab by ionic solution application [2304.05686].
- **2D e-beam:** Monolayer semiconductor (e.g., WSe$_2$), encapsulated in hBN, patterned and voltage-modulated under e-beam exposure [2512.06318].
- **Flexible-FET/DTMOS:** SOI double-gate with self-aligned bottom-gate; substrate or gate voltage source for dynamic $V_{th}$ tuning [1211.4564, 1003.6030].

### 3.2. Programming Protocols  
- **FeFET:** 1 μs programming pulses (2.6–7.6 V for HZO), up to 27 resolvable $V_{th}$ levels, programming window $\sim$1.3 V [2004.03903].
- **ISFET:** $V_{th}$ switched by exposure to pH 2–10 buffers; ∼30 s equilibration, 470 mV $V_{th}$ shift achievable, retention $\sim$10 h, $>100$ cycles [2304.05686].
- **e-beam:** 10–60 s exposure, writing $|\Delta V_{th}|$ up to $\sim$8.5 V, retention $>$24 h [2512.06318].
- **DTMOS/VTMOS:** $V_{AN}$ swept 0–0.2 V; voltage bias sets dynamic threshold, active only under supply [1003.6030].

### 3.3. Performance Metrics  
- **On/off ratio**: $10^4$–$10^6$ (TVD, FeFET, SWCNT FeFET), up to $10^7$ (e-beam WSe$_2$).
- **Endurance**: $>10^6$ (ferroelectric, TVD), $>10^2$ (ISFET), $>10$ (e-beam).
- **Read/program speed**: 1–25 ns (ferroelectric), $<1$ ms (ISFET verify), $<60$ s (e-beam write).
- **Retention**: Non-volatile (FeFET, e-beam), $>$10$^4$ s (SWCNT FeFET), $>$10 h (ISFET).
- **Power/delay**: VTMOS allows sub-300 pW per gate at $V_{DD}$=0.2 V, 50% power reduction vs. CMOS at $f<10$ MHz [1003.6030].

## 4. Circuit-Level Applications and Architectural Integration

### 4.1. Camouflaged and Reconfigurable Logic  
- TVD and ISFET-TVD gates achieve universal logic (NAND/NOR/AND/OR/XOR/XNOR/INV/BUF) by selective HVT/LVT assignment, obscuring function from physical layout [1512.01581, 2304.05686].
- FeFET and e-beam-written FETs enable in-field logic reconfiguration and hardware personalization; rewritable logic (e.g., NAND↔NOR) is demonstrated with threshold-polarity transitions [2512.06318].
- Flexible-FET and DTMOS/VTMOS enable adaptive logic where sub-threshold operation can dynamically vary the logic thresholds for energy efficiency [1003.6030].

### 4.2. Neuromorphic and Memory Functions  
- Multi-level threshold FeFETs function as artificial synapses for deep neural network online training, achieving $>$98% MNIST accuracy using device-level weight updates [2004.03903].
- Mott-FeFETs exploit an insulator-metal transition for decoupled program/read margins, $I_{bit1}/I_{bit0}\sim10^4$, and low-voltage operation [2108.12091].
- SWCNT/AlScN FeFETs realize compact, back-end-of-line-compatible ternary content-addressable memory with a single FET per cell, reducing area by 10$\times$ over CMOS implementations [2411.03198].

## 5. Materials, Interface Engineering, and Scalability

- Work-function engineering with low-defect dielectrics (e.g., ZrO$_2$/hBN) allows precise, tunable $V_{th}$ in monolayer MoS$_2$ FETs, circumventing pinning observed in HfO$_2$ [2512.20069].
- Standard ALD/PVD and transfer processes support integration of ferroelectric films and aligned nanomaterials (SWCNTs, 2D TMDs), with BEOL compatibility (T$<$400$^{\circ}$C) [2411.03198].
- Interface chemistry (low $Q_{it}$, minimal $Q_{ox}$) is critical for achieving linear and reproducible $V_{th}$ modulation, especially in gate-stack and 2D FETs [2512.20069].
- Fluidic and e-beam programming depend on charge-trap stability and environmental retention; volatile modes are suited to tamper-evidence or temporary logic reconfiguration.

## 6. Security and Hardware Obfuscation

- Threshold-programmable switches in TVD/ISFET-TVD cells resist physical/netlist reverse engineering, as $V_{th}$ state is invisible to standard imaging [1512.01581, 2304.05686].
- ISFET-TVD provides post-manufacture personalization (hardware PUFs, in-field role transformation) by re-exposing passivation to alternate pH solutions [2304.05686].
- Even a modest fraction of gates implemented as threshold-programmable (e.g., 1% out of 10k gates) yields brute-force security times exceeding $10^5$ years at 1 GHz test rates [1512.01581].

## 7. Limitations and Future Directions

- Ferroelectric devices, while non-volatile, may exhibit endurance limits ($10^6$–$10^9$ cycles) and require high programming voltages (typically $>$2–4 V), although SWCNT/FeFET and Mott-FeFET examples show progress on voltage scaling [2108.12091, 2411.03198].
- ISFET fluidic programming is limited by retention ($\sim$10 h) and surface chemical drifts (≈5–10 mV per decade), but enables field-reconfigurability not feasible with implanted-doping-based TVD [2304.05686].
- Dynamic body-biasing (VTMOS/DTMOS) and Flexible-FETs deliver ultra-low-power operation at the expense of speed, area, and reliability overhead for body-bias generation [1003.6030].
- A key research focus is extension to 2D materials (WSe$_2$, MoS$_2$) where native interfaces allow threshold tuning without chemical doping, defect manipulation, or high-temperature processing [2512.20069, 2512.06318].
- Integration, uniformity, and scaling challenges are prominent in large-area arrays and in co-design for neuromorphic and security primitives.

---

*See: [2004.03903], [2411.03198], [2304.05686], [1512.01581], [1211.4564], [2108.12091], [2512.20069], [2512.06318], [1003.6030]*.

Source: https://www.emergentmind.com/topics/threshold-programmable-fets