--- title: 'TernaryLM: Efficient Ternary LLM Quantization' url: https://www.emergentmind.com/topics/ternarylm type: topic --- # TernaryLM: Efficient Ternary LLM Quantization A Ternary Language Model (TernaryLM) is a language model whose parameters— and, in some systems, activations—are quantized to the ternary alphabet $\{-1, 0, +1\}$. The motivation for TernaryLMs is to drastically reduce memory footprint, energy consumption, and computational complexity compared to conventional 8–16-bit or floating-point LLMs, while retaining a substantial fraction of their language modeling, reasoning, and transfer capabilities. TernaryLM research encompasses quantization-aware training, post-training quantization, advanced packing/compression schemes, hardware/FPGA/ASIC/CPU/GPU kernel design, and scaling law analysis. Despite the apparent extremeness of 1-bit (ternary) quantization, careful algorithmic and systems co-design enables these models to approach full-precision performance in key metrics such as perplexity, downstream task accuracy, and inference throughput [2602.07374][2506.23025][2406.07177][2504.06298][2509.13765][2504.16266][2511.13676][2606.13054][2604.20913]. ## 1. Ternary Quantization Methodologies and Theory Ternary quantization constrains weights (and sometimes activations) to the set $\{-1, 0, +1\}$. The basic mapping for a real-valued parameter $w$ is: \[ \hat{w} = \alpha \cdot \mathrm{sign}_\tau(w) \] where $\alpha$ is a learned or per-group/channel scale and the ternary sign function applies a threshold $\tau$: \[ \mathrm{sign}_\tau(x) = \begin{cases} +1 & x > \tau \\ 0 & |x| \le \tau \\ -1 & x < -\tau \end{cases} \] Sophisticated methods extend this mapping by introducing learnable channel-wise shifts (DLT) [2406.07177], asymmetric thresholds, or signed-zero states (SZT, a 2-bit extension providing two bit-exact "zero" codes for enhanced backward signal) [2508.05905]. Ternarization may be applied during post-training quantization (PTQ) [2406.07177][2506.01140][2606.13054], quantization-aware training (QAT) [2602.07374][2506.23025][2506.01140], or via hybrid approaches. Training often leverages the straight-through estimator (STE) so that gradients are not zeroed out by the piecewise-constant ternary function. TWLA [2606.13054] incorporates Kronecker-structured orthogonal transformations ("rotation-domain shaping") to induce ternary-friendly tri-modal distributions in both weight and activation statistics, enabling stable joint quantization of weights to 1.58 bits and activations down to 4-bit. Signed-Zero Ternary (SZT) [2508.05905] generalizes balanced ternary by splitting the dead-zone zero state into “$+$” and “$-$,” providing one extra bit of sign information for improved gradient flow during QAT. ## 2. Training, Post-training Quantization, and Optimization TernaryLMs can be either: - **Quantized from full-precision checkpoints**: PTQ methods such as E2M-ATQ [2606.13054], DLT + OFF [2406.07177], and asymmetric ternarization [2506.01140] optimize scale, shift, and thresholds to minimize pre- and post-activation errors, often using calibration data to relocate centroids and assess bit allocation (e.g., via ILA-AMP [2606.13054]). - **Trained natively under ternary constraints**: TernaryLM [2602.07374] and Spectra 1.1 [2506.23025] incorporate quantization in their forward computation, adapt scaling factors per-layer (or per-group), and propagate gradients with STE. This approach eliminates the post-training conversion step and enables the model to adapt to the quantization regime "from scratch." Key optimization features include: per-neuron or per-channel scaling factors, per-channel shift, dynamic thresholds (often a fraction of activation or weight statistics), and dual-stage clustering or K-means for initialization [2504.06298][2406.07177]. E2M-ATQ [2606.13054] uses a two-stage process, first minimizing reconstruction loss in weight space, then relocating weight centroids on the manifold to directly minimize the layer's output error under the calibrating activation statistics. KOTMS rotation [2606.13054] and similar rotation-domain approaches [2603.27914] quantitatively shape the weight (and activation) distribution to maximize the efficiency of ternary codes. ## 3. Memory, Compute, and Information Efficiency Ternary quantization offers a theoretical storage requirement of $\log_2(3) \approx 1.585$ bits/weight. Practical implementations approach this bound via packed encodings (e.g., five ternaries per byte [2506.23025][2509.13765]). Hybrid formats use 2 bits/weight (for fast decoding [2504.16266][2511.13676], sometimes augmented with per-row or per-channel scales), or 1.6 bits/weight for optimal entropy packing [2506.23025][2504.16266][2509.13765]. For a 132 M parameter TernaryLM [2602.07374], memory usage drops from 1.2 GB (FP32 BERT-Base) to 498 MB, a 2.4× reduction. Tenet and TeLLMe demo 64 B → 80 B decompression for storage-optimal inference on FPGAs and ASICs [2509.13765][2504.16266]. Compute savings arise because ternary dot products need no multiplications (only adds and subtracts), reducing energy per operation by ∼5× over FP16 [2406.07177][2604.20913]. On CPUs and FPGAs, multiplication-free matmul kernels yield 30× speedup in GEMV/GEMM kernel latency and drive the system from memory-bound to compute-bound regimes [2604.20913][2511.13676][2504.16266]. Specialized kernels exploit AVX-512 (FairyFuse [2604.20913]), CPU SIMD with in-register LUTs (T-SAR [2511.13676]), and custom table-LUT matmul (TeLLMe [2504.16266], TENET [2509.13765]). Packing Efficiency Table: | Scheme | Bits/Weight | Comment | |-----------------|-------------|-------------------------------------| | Naive ternary | 2.0 | Direct 2-bit encoding [2604.20913] | | Base-3 packing | 1.6 | Entropy-optimal, 5/byte [2506.23025][2509.13765] | | ITQ3_S | 3.125 | Ternary in rotation domain [2603.27914] | ## 4. Model Quality, Scaling, and Task Performance Empirical findings indicate that TernaryLMs achieve high accuracy on both pretraining and downstream tasks with only moderate perplexity overhead. For example: - TernaryLM (1-bit native QAT) obtains PPL 58.42 (TinyStories), MRPC F1 82.47, SST-2 88.92, CoLA 47.23, with 2.4× reduction in memory [2602.07374]. - TernaryLLM (W1.58A16) on LLaMA-3-8B achieves PPL(C4)=13.4 versus DB-LLM’s 19.2 (W2A16) [2406.07177]. - TWLA (W1.58A4) on LLaMA2-13B achieves 86.4 tok/s at 3.3 GB and 58–73% accuracy on zero-shot tasks, recovering ∼80–92% FP16 performance [2606.13054]. - Spectra-1.1 TriLMs (QAT ternary) retain full-precision scaling law behavior, with only a +0.02 nats/token irreducible loss gap, and downstream MMLU accuracy equal or superior to FP16 baselines in the 1–3B parameter regime [2506.23025]. Layer-wise analysis shows that middle transformer blocks achieve the highest sparsity (∼60–62%), enabling more aggressive quantization in these layers without severe performance loss [2602.07374]. Scaling law fits in Spectra-1.1 further indicate that, under aggressive ternary quantization, data scaling is notably more profitable than parameter scaling—suggesting large-token-count pretraining is essential [2506.23025]. ## 5. Accelerator, Kernel, and Inference System Design TernaryLMs require highly specialized hardware or kernel support to unlock their efficiency. Key developments include: - **FPGAs/ASICs**: Table-LUT matmul (TeLLMe [2504.16266]), sparse ternary LUT cores (TENET [2509.13765]), full on-chip and HBM-assisted dataflows (TerEffic [2502.16473]), and 64 B→80 B base-3 decompression for storage-optimal decoding [2509.13765]. - **CPUs**: FairyFuse fuses all matrix-vector multiplications in a Transformer block into a single AVX-512 loop with zero multiplies, achieving 32.4 tok/s on a Xeon 8558P (WikiText-2 PPL gap to FP16 is only +0.05) [2604.20913]. T-SAR introduces in-register LUTs and novel SIMD instructions (TLUT, TGEMV) for dynamic kernel construction, avoiding memory LUT bottlenecks and yielding up to 24.5× GEMM latency reduction [2511.13676]. - **GPUs**: TriRun (Spectra 1.1 [2506.23025]) fuses INT2 weight unpacking and matmul with double-buffered, tile-based shared-memory loading, exploiting tensor core throughput for more than 5× layer throughput over FP16 baselines. Key architectural innovations include dynamic activation sparsity via N:M block schemes [2509.13765], rotation-domain shaping [2603.27914], and fused normalization–quantization pipelines minimizing off-chip traffic [2504.16266]. ## 6. Fault Tolerance, Reliability, and Edge Deployment TernaryLMs are well-positioned for deployment on resource-limited and unreliable hardware. ReTern exploits redundancy in ternary codes and column-wise sign flipping to achieve up to 35% perplexity reduction under 10% stuck-at-faults in compute-in-memory (CiM) accelerators with <3% overhead [2506.01140]. Practical systems such as TeLLMe and TENET demonstrate real-time inference (10–16k tok/s) and energy efficiency up to 21× over NVIDIA A100 on edge FPGAs and ASICs, with full prefill and decoding support [2504.16266][2509.13765][2502.16473]. CPU-based frameworks (T-SAR) provide viable alternatives to NPU and FPGA for platforms with only SIMD units, unlocking up to 8×–13× speedups over previous software kernels on mainstream x86 and ARM edge devices [2511.13676]. ## 7. Limitations, Open Challenges, and Future Research Remaining challenges include: - **Activation quantization**: Most practical TernaryLMs retain FP16/INT8 activations owing to catastrophic errors from outlier spikes; only TWLA demonstrates stable 4-bit activation quantization with ternary weights [2606.13054]. - **Extreme outlier handling**: Dual learnable scale/shift (DLT), orthogonal/rotation domain shaping, and group-wise threshold adaptation mitigate but do not eliminate performance losses from highly asymmetric outliers [2606.13054][2406.07177][2603.27914]. - **Hardware support**: Full realization of the theoretical efficiency requires hardware support for ternary arithmetic, bit-fused LUTs, or custom packing/decoding, which is only partially available in present CPUs/GPUs/NPUs. - **Model architecture generality**: Most results are demonstrated on decoder-only transformer LLMs; extending TernaryLMs to encoder-decoder or retrieval-augmented architectures is an open avenue [2406.07177][2602.07374]. - **Scalability**: TernaryLMs exhibit unique scaling law behaviors—efficient scaling with data, not just model size—and methods for trillion-parameter TernaryLMs are under active investigation [2506.23025]. - **Joint weight-activation quantization**: Co-design of ternary weights and low-bit (≤4b) activations remains at research frontiers, with only TWLA showing practical high-accuracy joint quantization [2606.13054]. Empirical and analytical research continues on mixed-precision policies, hybrid codebooks (e.g., SZT [2508.05905]), edge-device kernels, and hardware-fault adaptive quantization [2506.01140][2506.23025][2506.13054]. Source: https://www.emergentmind.com/topics/ternarylm