--- title: Split Integer Emulation of FP64 url: https://www.emergentmind.com/topics/split-integer-emulation-of-fp64 type: topic --- # Split Integer Emulation of FP64 Split integer emulation of FP64 refers to a class of numerical methods in which double-precision floating-point arithmetic (IEEE 754, 64-bit) is emulated by decomposing FP64 values and operations into lower-precision integer or floating-point computations, then recombining the results using algorithmic procedures. These techniques exploit high-throughput, low-precision hardware units—such as INT8/FP8 Tensor Cores on modern GPUs—to efficiently perform large-scale computations that require FP64 accuracy. The result is often substantial performance and energy benefits, with application to scientific computing, dense matrix operations, and numerical linear algebra. ## 1. Foundational Principles The central idea of split integer FP64 emulation is to represent each FP64 number (and, by extension, FP64 operations) as a structured combination of low-precision segments—typically 8- or 16-bit integers or floating-point blocks—which are processed independently using hardware-accelerated routines. The emulation relies on error-free transformations or controlled-sum algorithms, such that the final recombination step restores the full FP64 precision. A canonical form for splittings is: \[ a = \sum_{i=0}^{s-1} a^{(i)} \cdot \alpha^{i}, \] where $a^{(i)}$ are the split components (e.g., INT8 values) and $\alpha$ is a power-of-two scaling factor. For two numbers $a$ and $b$, products can be expanded as: \[ a \cdot b = \sum_{i,j} a^{(i)} b^{(j)} \alpha^{i+j}, \] with each $a^{(i)} b^{(j)}$ computed in low-precision and later accumulated using high-precision or error-free techniques [2509.23565, 2306.11975]. ## 2. Split Emulation Methodologies ### 2.1 Table-Lookup Emulation for Subsets For data files storing numbers with limited significant digits, a subset of FP64 values is exactly representable in a compact 32-bit form. The technique involves storing the sign, exponent, and high-order mantissa bits and reconstructing the remaining mantissa bits from a lookup table parameterized by selected bitfields [1504.02914]. Encoding is a direct copy of the upper 32 bits; decoding is via a fast table lookup using a subset of mantissa/exponent bits: \[ \text{index } i = \text{mantissa}(t)_{0..(m-1)} + [\text{exponent}(t)_{f..(f+e-1)} << m]. \] This enables rapid, memory-efficient storage and fast reconstruction of FP64 values for large arrays, particularly in scientific data with limited precision. ### 2.2 Slicing and GEMM-based Emulation For dense matrix multiplication, the Ozaki scheme and its variants ("shared-place" or "multi-slice") systematically split input matrices $A$, $B$ into $s$ components, mapping the mantissa via bit-level or fixed-point transformations. Each slice is processed using low-precision units (e.g., INT8 Tensor Cores), with the products scaled and summed according to block exponents [2306.11975]. The generic computation is: \[ C = \sum_{i+j \leq s+1} A^{(i)} B^{(j)} \odot \left(2^{-(i+j)\alpha}\, e_A\, e_B^{\top}\right), \] where $\odot$ denotes element-wise scaling and $\alpha$ is selected based on accumulator round-off and inner-product length. ### 2.3 Modular and CRT-based Methods Ozaki Scheme II generalizes emulation via the Chinese Remainder Theorem (CRT). Matrices are first scaled to integers (via diagonal matrices $D$, $E$), then reduced modulo $s$ pairwise coprime integers $m_1,\ldots,m_s$. Modular products are computed using INT8 or other supported tensor core units. CRT is used to reconstruct the full product modulo $M = m_1 m_2 \cdots m_s$: \[ X \equiv \sum_{i=1}^s C_i\,M_i\,y_i \pmod M, \] where $M_i = M/m_i$, $y_i = M_i^{-1} \pmod{m_i}$, and the final step inverts the original scaling to map results back to the FP64 domain [2504.08009]. ## 3. Hardware Mapping and Performance Split FP64 emulation leverages dedicated low/high-throughput units as follows: | Hardware Unit | Role in Emulation | Key Benefits | |-----------------------|------------------------------------|-----------------------------| | INT8/INT32 Tensor Core| Matrix multiplications for slices | Throughput, energy savings | | FP8/FP16 Tensor Core | Alternative for slicing & GEMM | Wider dynamic range (FP8) | | CPU SIMD INT ops | Quadruple or extended precision | Efficient for small/special sizes | On GPUs such as NVIDIA Hopper or Blackwell, INT8-based emulation achieves FP64-equivalent DGEMM throughput significantly higher than vendor-supplied FP64 BLAS, e.g., 7.4–9.8 TFLOPS on NVIDIA RTX 4090 and 56.6–80.2 TFLOPS on GH200 (Ozaki Scheme II) [2504.08009]. Integer-based approaches also reduce memory overhead by shared exponents and block operations, with working memory reductions of up to 50–75% compared to conventional FP16/FP32 methods [2306.11975]. Power consumption is reduced due to the lower energy cost per operation of INT8 units [2509.23565]. ## 4. Numerical Properties and Challenges Split integer emulation introduces nonstandard numerical characteristics relative to hardware FP64: - **Quantization and Range:** INT8/FP8 segments have limited dynamic range. The splitting strategy must prevent overflow, and scaling must preserve significant digits under worst-case input spread [2509.23565]. - **Accumulation Errors:** Summing partial products in low-precision can lead to cancellation, especially for ill-conditioned problems. High-precision (often FP64) accumulation or block-wise compensation is required. - **Error Propagation:** Multiple slices and recombinations increase complexity of tracking rounding error. Error-free or compensated summation helps mitigate accumulation of numerical errors. - **Modulo Constraints (CRT-based):** The modular product space must exceed twice the dynamic range of intermediate results to ensure uniqueness in CRT recovery: $2c_\text{max}