---
title: Spin Shuttling in Semiconductor Qubits
url: https://www.emergentmind.com/topics/spin-shuttling
type: topic
---

# Spin Shuttling in Semiconductor Qubits

Spin shuttling is the coherent transport of a spin qubit’s quantum state by physically moving the carrier between sites in a semiconductor device, typically a single electron in silicon or a single hole in germanium quantum dots, while preserving spin population and, in the fully coherent regime, phase. In gate-defined semiconductor architectures, it functions as a hardware-native quantum link between spatially separated qubit registers, relieving the wiring bottleneck, enabling sparse and modular layouts, and providing an alternative to static exchange chains, resonator-mediated coupling, and surface-acoustic-wave transport [2209.00920]. Two broad implementations dominate the literature: “bucket brigade” transport, in which the carrier is transferred stepwise through successive interdot anticrossings, and conveyor-mode shuttling, in which a traveling electrostatic minimum carries the carrier continuously along a channel [2502.20955].

## 1. Physical principle and transport modalities

In the bucket-brigade mode, an electron is moved by sequentially adjusting electrochemical potentials so it adiabatically follows the ground state through successive interdot anticrossings. In a representative silicon implementation, each hop consists of an abrupt pulse to a point just before an interdot anticrossing in detuning $\epsilon$, a linear ramp through the anticrossing over $\Delta\epsilon \approx 300~\mu\mathrm{eV}$ in $\tau_{\mathrm{ramp}} = 2~\mu\mathrm{s}$, and an abrupt pulse well past the anticrossing to suppress back-tunneling [2209.00920]. This mode is tolerant to local disorder and fits naturally into one-dimensional or two-dimensional dot arrays fabricated with standard Si/SiGe gate stacks [2209.00920].

In conveyor-mode shuttling, the confining potential itself is translated. A conventional implementation uses phase-shifted sinusoidal gate voltages, while later work introduced digitally synthesized near-sinusoidal waveforms and two-tone traveling-wave potentials [2502.20955]. In four-phase wiring with pitch $l_{\mathrm{pitch}}$, the traveling potential advances $4 l_{\mathrm{pitch}}$ per period, so $f = v_{\mathrm{avg}}/(4 l_{\mathrm{pitch}})$ and $f_{\mathrm{clk}} = 4 f$ in the cryogenic integrated implementation [2604.20482]. Conveyor-mode is attractive when the objective is long, resource-efficient channels controlled by a small number of global phases [2209.00920].

The architectural motivation is consistent across platforms. Coherent links spanning tens of micrometers are expected to interconnect sparse clusters of spin qubits while leaving on-chip area between clusters for classical control electronics, including cryo-CMOS multiplexers, DACs, and resonators [2209.00920]. This creates a routing primitive that can be concatenated over longer distances and reduces the number of off-chip interconnects required in large arrays [2209.00920].

## 2. Dynamical models, adiabaticity, and coherence

Near an interdot anticrossing, bucket-brigade shuttling is described by the standard two-level Hamiltonian
$$
H = (\epsilon/2)\sigma_z + t \sigma_x,
$$
with detuning $\epsilon$, tunnel coupling $t$, and anticrossing gap $2t$ [2209.00920]. Charge-transfer adiabaticity is commonly analyzed with the Landau–Zener expression
$$
P_{\mathrm{LZ}} = \exp\!\left(- \frac{2\pi \Delta^2}{\hbar v}\right),
$$
where $\Delta \approx t$ is half the minimum gap and $v = d\epsilon/dt$ is the sweep rate [2209.00920]. In the four-dot silicon array of [2209.00920], $t/h \approx 3$–$7~\mathrm{GHz}$ and $v \approx 150~\mathrm{eV/s}$ give $2\pi\Delta^2/(\hbar v) \gg 1$ and thus $P_{\mathrm{LZ}} \ll 10^{-100}$, so charge transfer is overwhelmingly adiabatic.

Conveyor-mode silicon shuttling introduces a second adiabaticity problem associated with the valley degree of freedom. In a valley-aware description, the joint spin–valley dynamics is governed by
$$
H(t) = H_S + H_V(x_{\mathrm{qd}}(t)) + H_{VS}(x_{\mathrm{qd}}(t)),
$$
with $H_S = (E_Z/2)\sigma_z$, $H_V(x_{\mathrm{qd}})=\Delta_r(x_{\mathrm{qd}})\tau_x+\Delta_i(x_{\mathrm{qd}})\tau_y$, and $H_{VS}(x_{\mathrm{qd}})=-\kappa_z \tilde{\tau}_z(x_{\mathrm{qd}})\otimes \sigma_z$ [2604.20482]. Here the local valley splitting is $E_v(x_{\mathrm{qd}})=2|\Delta(x_{\mathrm{qd}})|$, and small-$E_v$ regions amplify non-adiabatic valley excitation and spin–valley entanglement [2604.20482]. This is the dominant theoretical explanation for why long conveyor paths in disordered Si/SiGe require velocity shaping, path selection, or heterostructure engineering [2405.01832].

In germanium hole systems, strong spin–orbit interaction makes the local quantization axis itself dot-dependent. Experiments therefore distinguish ramps that are diabatic with respect to the spin quantization axis but adiabatic with respect to charge transfer from ramps that are adiabatic with respect to both [2308.02406]. In that setting, the relevant phase is
$$
\varphi(T)=\int_0^T \omega_L(t)\,dt,\qquad \omega_L(t)=\frac{g(t)\mu_B B}{\hbar},
$$
so dot-to-dot $g$-tensor variations directly produce phase shifts that must be calibrated or dynamically refocused [2308.02406].

A third line of theory treats motion itself as a resource for decoupling. In planar germanium, temporal and spatial “breathing” protocols modulate the confinement potential during shuttling so that spin–orbit interaction generates a continuous resonant drive, implementing dressed-state transport and continuous dynamical decoupling [2605.00611]. This does not change the definition of spin shuttling, but it broadens the control space from trajectory design alone to trajectory-plus-confinement design.

## 3. Experimental realizations and representative benchmarks

The experimental literature spans GaAs, Si/SiGe, Si MOS, and Ge/SiGe, with distinct trade-offs between hyperfine noise, spin–orbit interaction, valley physics, and control bandwidth.

| Platform and modality | Representative result | Citation |
|---|---|---|
| GaAs quadruple-dot coherent shuttle | S–T$_0$ oscillations after shuttling to dot 2, 3, or 4 with $f = 103 \pm 5$, $118 \pm 7$, and $185 \pm 14~\mathrm{MHz}$ | [1701.00815] |
| Silicon four-dot bucket brigade | Up to $1000$ hops ($\approx 80~\mu\mathrm{m}$) with spin-flip probability per hop well below $0.01\%$ | [2209.00920] |
| Germanium hole-spin bucket brigade | Basis-state shuttling length $L_{\mathrm{spin}} \approx 312~\mu\mathrm{m}$; coherent superposition length $L_{\mathrm{coh}} \approx 49~\mu\mathrm{m}$ with echo | [2308.02406] |
| Silicon conveyor-mode moving dot | Effective $10~\mu\mathrm{m}$ displacement in $184~\mathrm{ns}$ with $F_{\mathrm{sh}} = 99.07 \pm 0.13\%$ | [2406.07267] |
| Silicon MOS bucket brigade | Average shuttling fidelity $F_{\mathrm{sh}} \approx 99.77\%$, consistent with a $99.8\%$ headline result | [2507.15554] |

The GaAs work established the core coherence criterion: after separating one electron from a singlet and shuttling it to dots 2, 3, or 4, the separated state evolved periodically into $T_0$ and back, showing that relative spin phase survived spatial transport [1701.00815]. The silicon four-dot experiment then demonstrated repeated forward–backward shuttling up to $250$ rounds through three dots and $90$ rounds through four dots, with no detectable number-dependent accumulation of spin flips up to $1000$ hops in the main dataset and $2000$ hops in additional data [2209.00920].

The germanium study is notable because it achieved coherent shuttling despite strong spin–orbit interaction and large dot-to-dot quantization-axis changes, with at least $42^\circ$ tilt between QD2 and QD3 and at least $33^\circ$ between QD3 and QD4 [2308.02406]. The main limitation there was dephasing rather than shuttling-induced flips, and Hahn echo extended coherent transport from $L_{\mathrm{coh}} \approx 9~\mu\mathrm{m}$ to $L_{\mathrm{coh}} \approx 49~\mu\mathrm{m}$ [2308.02406]. This directly contradicts the common simplification that strong spin–orbit interaction is necessarily incompatible with coherent shuttling.

The silicon conveyor comparison in [2406.07267] sharpened the distinction between bucket-brigade and moving-dot transport. Bucket-brigade shuttling across dots 2 to 5 gave average per-hop return probability $99.43 \pm 0.02\%$ in Ramsey and $99.72 \pm 0.01\%$ in Hahn echo, but $T_2^*$ degraded to $\approx 1.04~\mu\mathrm{s}$ during hopping relative to static dots [2406.07267]. Conveyor-mode transport, especially the two-tone conveyor, showed better spin coherence during motion and enabled the $10~\mu\mathrm{m}$, $184~\mathrm{ns}$ benchmark [2406.07267].

## 4. Error channels and fidelity-limiting mechanisms

In isotopically enriched silicon, the dominant observed decay in repeated bucket-brigade experiments is typically not spin-flip transport error but relaxation during waiting periods. In the four-dot Si/SiGe array, the measured $T_1$ values at $B_0 = 1.3~\mathrm{T}$ were $129 \pm 33~\mathrm{ms}$, $257 \pm 79~\mathrm{ms}$, and $152 \pm 48~\mathrm{ms}$ for dots 1, 2, and 3, and the weighted three-dot value was $170 \pm 18~\mathrm{ms}$ [2209.00920]. Exchange with reservoirs was suppressed by a dot–reservoir tunnel rate of $\approx 32~\mathrm{kHz}$, hyperfine-induced flips by $^{28}$Si enrichment with $\sim 800$ ppm residual $^{29}$Si, and spin–orbit mediated flips by the absence of a micromagnet and the use of adiabatic ramps [2209.00920].

In silicon MOS bucket-brigade transport, the dominant residual error was instead dephasing during detuning sweeps near charge-transfer regions, and the error changed by up to a twenty-fold variation as the ratio $2 t_c/E_Z$ was tuned across the crossover where $2 t_c \approx E_Z$ [2507.15554]. The underlying four-level model shows that when $2 t_c \gg E_Z$ and $2 t_c \gg |\delta E_Z|$, the effective qubit splitting becomes flat in detuning near the transition and both charge-noise sensitivity and parasitic spin-flip channels are suppressed [2507.15554].

For long conveyor paths in Si/SiGe, valley disorder dominates. In the random-alloy-disorder picture, the intervalley coupling $\Delta(x,y)$ forms a random complex field, and contours where $\mathrm{Re}[\Delta]=0$ and $\mathrm{Im}[\Delta]=0$ intersect at points where $E_v=0$ [2405.01832]. This means that in the disordered regime, pockets of very small valley splitting are unavoidable along sufficiently long paths [2405.01832]. The mitigation strategies explicitly demonstrated are heterostructure modification, vertical electric-field tuning, shuttling-velocity modulation, dot elongation, and path planning via channel shifting [2405.01832]. In $3~\mathrm{nm}$ and $5\%$ Ge quantum wells, the combination of channel shifting, velocity modulation, and dot elongation brought $10~\mu\mathrm{m}$ shuttling infidelities below $10^{-3}$ for the majority of disorder realizations [2405.01832].

A complementary result is that strong mitigation need not require precise knowledge of every valley near-degeneracy. Few-parameter trajectory shaping with as few as $4$ Fourier components reduced the median infidelity for $10~\mu\mathrm{m}$ shuttling to approximately $10^{-3}$ at $v=2~\mathrm{m/s}$, while $M=9$ components at $v=5~\mathrm{m/s}$ reached approximately $2\times 10^{-4}$ [2409.07600]. This suggests that a low-dimensional control basis can capture the dominant disorder-averaged error mechanisms without full microscopic retargeting.

At the hardware level, the 2026 cryogenic-electronics study combined disorder-informed valley maps, transistor-level noise simulations, and a discrete resistor ladder controlling period-wise velocity modulation [2604.20482]. At $v_{\mathrm{avg}} = 20~\mathrm{m\,s^{-1}}$ over $10~\mu\mathrm{m}$, the optimized protocol achieved an average shuttling fidelity of $99.99 \pm 0.007\%$, compared with $99.78 \pm 0.06\%$ for a constant-resistor baseline, with active analog power $\approx 9.8~\mu\mathrm{W}$ [2604.20482].

## 5. Shuttling as a gate primitive and control resource

Spin shuttling is not only a transport primitive. It can also serve as the mechanism by which two-qubit interactions are switched on and off. In a silicon triple-dot device, one qubit remained local while the second was shuttled between a sparse state $(1,0,1)$ and a coupled state $(1,1,0)$, changing the exchange interaction from $J \approx 0.89 \pm 0.10~\mathrm{kHz}$ to $J = 1.25~\mathrm{MHz}$ and producing an on/off ratio exceeding $1000$ [2202.01357]. With this shuttling-mode exchange control, a controlled-phase gate of fidelity $92.72 \pm 0.18\%$ was demonstrated by interleaved randomized benchmarking [2202.01357].

A distinct theoretical direction uses non-adiabatic shuttling between dots with inhomogeneous Landé $g$-tensors to generate single-qubit gates without high-frequency driving fields [2602.14782]. There the spin deviation acquired during a transfer is deliberately converted into a gate resource, and multiple rounds of bidirectional shuttling are summarized by an operator matrix that can implement Pauli-$X$, Pauli-$Y$, and a generalized Hadamard gate after suitable idling times [2602.14782]. This is conceptually different from exchange-gated shuttling, because the motion itself is the gate.

An even stronger claim appears in mobile-electron architectures: shuttling-based single-qubit gates can significantly outperform static EDSR-type pulsing by using larger spatial mobility to generate larger Rabi frequencies at smaller magnetic-field gradients [2403.00601]. In that framework, fidelities are bottlenecked by spin–valley physics rather than charge-noise-induced magnetic detuning, and quantum optimal control restores gate fidelities to at least $99.9\%$ across broad parameter regions and device ensembles [2403.00601]. A plausible implication is that the boundary between “transport” and “gate” operations becomes blurred once motion is used as a first-class control knob.

A common misconception is that spin shuttling must minimize Zeeman inhomogeneity at all costs. Theory for strongly spin–orbit-coupled systems argues the opposite in an important regime: a large inhomogeneity of the Zeeman field can stabilize the coherence of a moving spin state by filtering out the dominant low-frequency contributions of the charge noise [2311.15970]. That conclusion aligns qualitatively with dressed-state shuttling proposals based on confinement modulation in germanium hole qubits, where motion-induced continuous driving suppresses low-frequency magnetic and electric noise [2605.00611].

## 6. Architectural implications and fault-tolerant thresholds

The systems literature treats shuttling as an architectural primitive rather than a mere device capability. In silicon dot arrays, short quantum links on the order of $10$–$100~\mu\mathrm{m}$ free up area for on-chip classical electronics between qubit blocks and reduce the number of off-chip interconnects [2209.00920]. Conveyor-mode and bucket-brigade approaches are therefore often framed as complementary: bucket brigade is more tolerant to local disorder, whereas conveyor belts promise resource-efficient long channels with few global phases [2209.00920].

Digital-control proposals make this compatibility explicit. A cryogenic switch matrix plus first-order RC low-pass filters can synthesize near-sinusoidal conveyor waveforms from a small number of DC voltage levels, with wiring that scales with $N_{\mathrm{DC}}$ rather than with qubit number [2502.20955]. For favorable parameters, simulations yield per-hop leakage below $10^{-4}$ and show that local waveform synthesis can keep power in the few mW range even for $10^6$ qubits [2502.20955]. This is not a demonstration of a processor-scale machine, but it is a concrete control-theory argument that shuttling need not be wiring-prohibitive.

Surface-code analyses further weaken the assumption that shuttle errors must already be at the $10^{-4}$ level to be useful. In a SpinBus-motivated circuit-level model, the shuttle noise is introduced as an extra “bus” error location on ancillas before each CZ [2503.10601]. At a standard circuit error rate $\mathrm{cer} \approx 0.1\%$, the bus thresholds are approximately $1.5\%$ for unbiased depolarizing shuttle noise and approximately $4.5\%$ for fully biased dephasing shuttle noise [2503.10601]. The teraquop overhead baseline is approximately $5\times 10^3$ physical qubits per logical qubit at $\mathrm{cer} = 0.1\%$, and the overhead remains modest up to bus error rates of approximately $0.3\%$ in the unbiased case and approximately $1\%$ in the biased case [2503.10601]. This suggests that dephasing-dominated shuttling is substantially more fault-tolerant than naive per-hop targets alone would imply.

At the architectural-synthesis level, a one-dimensional shuttling bus tailored to the rotated surface code has been optimized with a mixed-integer model and a linear-time Zig-Zag heuristic [2510.17689]. Under the stated noise model, the synthesized architecture reaches logical error rates as low as $2\cdot 10^{-10}$ per round at code distance $21$ [2510.17689]. A different application, the Parity Architecture, uses a constant-depth four-step schedule of global vertical shuttles and horizontal nearest-neighbor interactions to implement Parity QAOA on a repeated unit-cell lattice [2403.09574]. These studies do not prove that large-scale shuttle-connected processors are solved, but they show that shuttling has already been elevated from device transport to compilation, scheduling, and threshold analysis.

Spin shuttling is therefore best understood not as a single protocol but as a family of transport-and-control mechanisms spanning adiabatic interdot transfer, moving-dot conveyor channels, motion-enabled gates, and hardware-aware optimal control. Across that family, the central technical theme is consistent: the charge motion itself is relatively easy to make adiabatic, while high-fidelity operation is determined by how well spin, valley, Zeeman inhomogeneity, and noise are co-designed.

Source: https://www.emergentmind.com/topics/spin-shuttling