---
title: Source Retention Loss in MIFIS FeFETs
url: https://www.emergentmind.com/topics/source-retention-loss-srl
type: topic
---

# Source Retention Loss in MIFIS FeFETs

Source Retention Loss (SRL) in ferroelectric field-effect transistors (FeFETs) employing a metal-insulator-ferroelectric-insulator-semiconductor (MIFIS) structure refers to the phenomenon where the programmed erase state (high threshold voltage, $V_{th}$) degrades over time due to loss of gate-injected charge. This process manifests as a progressive downward shift of the erase threshold voltage $V_{th,ERS}$ during stand-by, leading to a significant reduction in the memory window—often by approximately 50% over a 10-year extrapolated retention period. The instability of the erase arm is particularly prominent, severely challenging long-term nonvolatile storage applications in advanced 3D FE NAND architectures [2510.15275].

## 1. Definition and Manifestation of SRL in MIFIS-FeFETs

Source Retention Loss (SRL) is defined as the time-dependent reduction of the programmed erase state in MIFIS FeFET devices, specifically observed as a negative drift in the erase threshold voltage $V_{th,ERS}$ over retention periods spanning $10^4$–$10^5$ s and extrapolated up to 10 years. In practice, this retention loss can reduce the original memory window by up to 50%, with the erase arm exhibiting the greatest instability. This characteristic distinguishes SRL from general retention degradation seen in conventional ferroelectric structures and establishes it as a key reliability challenge in MIFIS-based nonvolatile memory [2510.15275].

## 2. Physical Mechanisms: Gate-Injected Charge De-Trapping vs. Ferroelectric Depolarization

In conventional MFIS devices, retention loss is predominantly attributed to the depolarization field $E_{dep} = P_S / \epsilon_{FE}$, causing relaxation of the ferroelectric polarization ($P_S$). However, in MIFIS-FeFETs, Han et al. demonstrated that SRL is not governed by ferroelectric depolarization but instead by the de-trapping of gate-injected charges ($Q_G$). During retention ($V_g = 0$ V), the internal bias divides into a negative voltage ($V_{FE} \approx -2.3$ V for $d_{G.IL}=3.4$ nm) supporting $P_S$, and a positive voltage ($V_{G.IL} \approx +3.2$ V) across the gate-side interlayer (G.IL), which promotes de-trapping of $Q_G$ either back to the metal gate (Path I) or toward the channel/interlayer (Path II).

No significant decay of $P_S$ is observed in gate-current ($I_g$) measurements during a read sweep ($0\to4.6$ V), indicating that ferroelectric depolarization is negligible for retention loss physics in this context. Instead, all observable $V_{th}$ shifts over retention are quantitatively accounted for by $Q_G$ de-trapping. This decouples charge loss mechanisms from ferroelectric relaxation in these systems [2510.15275].

## 3. Quantitative Relationships and Charge Extraction

SRL is characterized by distinctive charge ratios and quantitative behaviors:

- The total displacement charge at $V_{th}$ is expressed as $Q_{FE} = P_S + \epsilon_{FE} E_{FE}$, with $P_S$ obtained from $P$–$V$ loops (e.g., $P_S \approx 14\,\mu\text{C}/\text{cm}^2$) and $E_{FE}$ (e.g., $1.3$ MV/cm) extracted from polarization loop fits.
- The electric field in the gate-side interlayer, $E_{G.IL}$, derives from the slope of $V_{th,ERS}$ versus $G.IL$-EOT: $\mathrm{slope} = dV_{th,ERS}/d(d_{G.IL}) \approx 1.54$ V/nm, resulting in $E_{G.IL} = 1.54$ MV/cm.
- Gauss’s law gives the trapped charge fractions:
  \[
  Q_G = Q_{FE} - \epsilon_{G.IL} E_{G.IL} \\
  Q_C = Q_{FE} - \epsilon_{C.IL} E_{C.IL}
  \]
- For $d_{G.IL} = 1.7, 3.4, 5.5$ nm, it is determined experimentally that $Q_G \approx 170\%\,P_S$ and $Q_C \approx 130\%\,P_S$, independent of thickness.
- The shift in threshold voltage due to loss of trapped charge is given by:
  \[
  \Delta V_{th} \approx \Delta Q_G / C_{G.IL} = \Delta Q_G \cdot d_{G.IL} / (\epsilon_0 \epsilon_r)
  \]
  For SiO$_2$ G.IL ($\epsilon_r \approx 3.9$), $\Delta Q_G = -1\,\mu\text{C}/\text{cm}^2$ over retention results in $\Delta V_{th} \approx -2.9$ V per 3.4 nm G.IL [2510.15275].

| Parameter        | Experimental Value | Formula/Notes                                      |
|------------------|-------------------|----------------------------------------------------|
| $P_S$            | $14\,\mu\text{C}/\text{cm}^2$ | From $P$–$V$ loops on FeCAP             |
| $Q_G/P_S$        | $\approx 1.7$ (170%)| Independent of $d_{G.IL}$             |
| $Q_C/P_S$        | $\approx 1.3$ (130%)| Independent of $d_{G.IL}$             |
| $E_{G.IL}$       | $1.54$ MV/cm        | Slope of $V_{th,ERS}$ vs. $d_{G.IL}$              |

## 4. Band Structure, Trap Levels, and Detrapping Pathways

The energy-band diagram under retention ($V_g=0$) for MIFIS-FeFETs is:
TiN Metal – SiO$_2$ G.IL – Hf$_{0.5}$Zr$_{0.5}$O$_2$ FE – SiO$_2$ C.IL – Si.

A principal deep trap level, $E_t$, is positioned approximately 3.0 eV below the SiO$_2$ conduction band edge, providing a reservoir for $Q_G$. The two relevant charge loss pathways are:

- **Path I (to metal):** $\Delta E_I = E_t - E_F^{metal} + q V_{G.IL}$
- **Path II (to channel):** $\Delta E_{II} = [E_{C,Si} - E_t] - q V_{C.IL}$

As $d_{G.IL}$ increases, $E_t$ moves closer to the Si conduction band (due to $V_{C.IL}$ becoming more negative), decreasing $\Delta E_{II}$ (facilitating Path II) but increasing $\Delta E_I$ (hampering Path I). The dominant detrapping path thus transitions from Path I to Path II with increasing $G.IL$ thickness [2510.15275].

## 5. Dependence of Retention Time on Interlayer Thickness and Detrapping Kinetics

Retention time exhibits a non-monotonic dependence on the $G.IL$ thickness ($d_{G.IL}$). Charge emission (detrapping) is modeled using a non-radiative multiphonon (NMP) emission framework:

\[
\tau = \tau_0 \cdot \exp\left(\frac{E_B}{kT}\right),\quad 
E_B = \frac{(E_R - (E_C - E_t))^2}{4E_R}
\]

For $E_t = -3.0$ eV, $E_R = 0.36$ eV, $\tau_0 = 10^{-10}\dots 10^{-7}$ s:

- For thin $G.IL$ ($1$–$3$ nm), Path I dominates (detrapping times $\tau_I \sim 10^{-11}$–$10^{-7}$ s), inducing poor retention.
- For thick $G.IL$ ($>5$ nm), Path II prevails ($\tau_{II} \sim 10^{-6}$–$10^{-4}$ s), shifting the bias-dependence.
  
Thus, both excessively thin and thick $G.IL$ layers degrade retention: if too thin, rapid tunneling through Path I; if too thick, energy band alignment enables efficient Path II detrapping, each leading to suboptimal retention characteristics [2510.15275].

## 6. Material and Device Design Strategies for SRL Mitigation

Optimizing MIFIS-FeFETs for minimal SRL involves coordinated strategies targeting both charge injection and detrapping pathways, as follows:

- **Gate-interlayer (G.IL) engineering:** Adoption of materials with larger bandgap and higher conduction-band offset (e.g., SiN or Al$_2$O$_3$/HfO$_2$/Al$_2$O$_3$ stacks) elevates energy barriers for both detrapping paths.
- **Physical thickness and dielectric constant:** Employing a physically thicker but low-$k$ G.IL maximizes tunneling distance (suppressing Path I) while minimizing $C_{G.IL}$ to preserve a large memory window.
- **Ferroelectric layer tuning:** Moderate $P_S$ is essential—adequate for a large memory window yet avoiding excessive $Q_G$ injection that amplifies SRL risk.
- **Channel interlayer/Silicon interface tailoring:** Adjustments such as post-anneal nitridation help modulate $V_{C.IL}$, impeding Path II detrapping.

These design principles serve to maximize both $\Delta E_I$ and $\Delta E_{II}$, thus suppressing both detrapping paths and restoring 10-year retention capability while supporting memory window requirements suitable for 3D FE-NAND [2510.15275].

Source: https://www.emergentmind.com/topics/source-retention-loss-srl