---
title: Solid-Liquid Interdiffusion (SLID)
url: https://www.emergentmind.com/topics/solid-liquid-interdiffusion-slid
type: topic
---

# Solid-Liquid Interdiffusion (SLID)

Solid–Liquid Interdiffusion (SLID) is a wafer-level metallurgical interconnect technology in which a low-melting-point metal (typically Sn) intermixes via interdiffusion with a higher-melting-point metal (typically Cu) to form high-melting-point Cu–Sn intermetallic compounds (IMCs). Developed for fine-pitch, high-reliability interconnection in 3D integrated circuits and advanced pixel detector modules, SLID enables vertical stacking and integration without reflow of pre-existing bonds, surpassing conventional solder bump-bonding in both mechanical integrity and long-term thermal stability. Its implementation in major high-energy physics detector upgrades, such as those for the ATLAS experiment at the HL-LHC, demonstrates its suitability for ultra-thin, radiation-hard, high-density module applications [1109.3299][1310.5854][1202.6497][1210.7933][0805.0917].

## 1. Physical Principles and Metallurgy

SLID exploits the solid–liquid interdiffusion behavior of specific binary systems, with the Cu–Sn couple as the canonical implementation. Key stages are as follows:

- **Thermodynamics and Intermetallic Formation**: The binary Cu–Sn system features a eutectic at approximately 8–10 atomic % Sn (Tₑ ≈ 217 °C). SLID is performed at or just above the melting point of Sn. Upon heating, Sn liquefies and interdiffuses into Cu, initially forming Cu₆Sn₅ (η-phase, Tₘ ≈ 415 °C). Continued diffusion and eventual consumption of Sn leads to formation of Cu₃Sn (ε-phase, Tₘ ≈ 676 °C) at the interface. The final IMC joint thus has a melting point in excess of 600 °C. Subsequent processing steps at lower temperatures cannot remelt the bond [1109.3299][0805.0917].

- **Diffusion Kinetics**: The growth of the IMC layer is diffusion-limited, following a parabolic law. The interdiffusion coefficient $D(T)$ follows an Arrhenius dependence:

  $$
  D(T) = D_{0} \exp\left(-\frac{Q}{R T}\right)
  $$

  where $D_0$ is typically $\sim10^{-4}$ m$^2$/s and $Q$ ranges from 80–150 kJ/mol for Cu–Sn compounds. At processing temperatures (240–320 °C), $D(T)$ enters the $10^{-16}$–$10^{-14}$ m$^2$/s range, enabling full intermetallic conversion of a $\sim$3 μm Sn film within tens of minutes under several MPa pressure. The IMC thickness $x(t)$ evolves as $x(t) = [k_0 \exp(-Q / R T) t]^{1/2}$ [1109.3299][1202.6497][1210.7933][0805.0917].

## 2. Fabrication Workflow

The SLID process is highly modular and executed at the wafer or chip level for integration flexibility. The standard implementation comprises:

- **Surface preparation**: Wafer cleaning (organic solvents, RCA or HF dip), plasma activation, and deposition of a 100 nm TiW (or Ti/Cr) diffusion barrier on Al pads to prevent Cu migration [1310.5854][1210.7933].

- **Electroplated metallization**:
  - 5–15 μm Cu is plated on both sensor and ASIC pads.
  - 3–5 μm Sn is electroplated on one side only (sensor or ASIC) [1310.5854][1109.3299].

- **Bond alignment and assembly**: Chips and wafers are aligned (typ. <20 μm accuracy) and brought into contact. Precision is further enhanced using vernier patterns/electrical markers; chip-to-wafer placements achieved ≲10 μm residual error [1310.5854].

- **Thermal cycling and interdiffusion**: Heating ramps at 1–5 °C/min to 240–320 °C, dwell at bond temperature (typically 15–30 min under 1–5 MPa), Sn melts and reacts with Cu. No reflow step is required—full conversion to high-melting IMCs is achieved. Slow cooling (1–5 °C/min) minimizes thermal stress [1310.5854][1210.7933].

- **Wafer handling and thinning**: After bonding, chips can be thinned to 50–60 μm (front-end ASICs), especially when integrating Inter-Chip Vias (ICVs) for vertical signal routing [1109.3299][1202.6497].

| Step                | Material/Process    | Typical Thickness/Condition       |
|---------------------|--------------------|-----------------------------------|
| Diffusion barrier   | TiW/Ti/Cr sputter  | 50–100 nm                         |
| Cu seed/electroplate| Cu electroplating  | 5–15 μm                           |
| Sn layer            | Sn electroplating  | 3–5 μm (one side only)            |
| SLID thermal cycle  | 250–320 °C, 1–5 MPa| 15–60 min (Sn fully consumed)     |
| Wafer thinning      | Backgrind, CMP     | ~50–60 μm (for ICV integration)   |

## 3. Microstructure, Electrical, and Mechanical Characterization

The resulting SLID interconnect exhibits:

- **Microstructure**: Cross-sectionally, IMC joints show a bilayer structure of Cu₆Sn₅ (adjacent to Cu) and Cu₃Sn (near Sn source), total thickness ∼3 μm. Grain sizes are sub-micron to several hundred nanometers. The process suppresses voiding and Kirkendall porosity when clean surfaces and pressure uniformity are maintained [1202.6497][0805.0917].

- **Electrical Performance**: Contact resistivity per SLID pad is 0.25–1.5 Ω (dominated by Cu–Al interface), with values <1 mΩ·cm². Modules exhibit low leakage ($<0.1$ μA), high breakdown ($>120$ V), and noise/threshold characteristics statistically equivalent to bump-bonded assemblies [1109.3299][1310.5854][1202.6497].

- **Mechanical Robustness**: Typical pull/shear strength is ∼0.01 N per pad ($>10$ MPa for industrial samples, 25–40 MPa for optimized Cu₃Sn). Failure occurs in the electroplated metal, not the IMC. SLID joints remain intact after 1000+ thermal cycles (–40 to +125 °C), irradiation up to $10^{16}$ n$_\mathrm{eq}$/cm², and back-end processing [1310.5854][1210.7933][0805.0917].

## 4. Integration with Inter-Chip Vias (ICVs) and 3D Stacking

The principal technological advantage of SLID is the ability to support sequential vertical stacking due to the high remelt temperature of the IMC. Modules fabricated at Fraunhofer EMFT combine SLID with ICVs (via-last, 3×10 μm², 60 μm depth, W-filled), enabling:

- **Vertical signal routing**: Signals traverse the thinned ($\sim$50 μm) FE-I3 chip to new backside pads, removing wire-bond cantilevers and enabling true four-side buttable module geometry [1109.3299][1310.5854][1202.6497].

- **Stackability**: Additional processing—such as further SLID or TSV bonding—can proceed at <400 °C, preserving previous SLID joints.

- **Fine pitch and low dead area**: SLID’s lithographically-defined rectangular pads permit pad pitches down to 20 μm, limited by pick-and-place accuracy, significantly below standard bump-bonding ($\geq$25 μm) [1310.5854][1210.7933].

- **Yield and planarity**: SLID yield exceeds 99.5% when planarization and passivation openings are well controlled; per-bond failure probability is typically <5×10⁻⁴ [1310.5854].

## 5. Performance Under Extreme Conditions: Radiation and Thermal Cycling

Comprehensive studies have validated SLID’s stability for cutting-edge detector requirements:

- **Radiation hardness**: No increase in disconnected channels or degradation in noise threshold post-irradiation up to $1\times10^{16}$ n$_\mathrm{eq}$/cm². Charge collection remains at ≥90% (CCE) at bias voltages <500 V even after highest fluences [1310.5854][1210.7933]. Mechanical and electrical properties of the interconnect are unchanged after repeated cycles and high-fluence neutron/proton irradiation [1109.3299].

- **Thermal cycling**: SLID joints survive >1,000 thermal cycles (–40 °C to +125 °C) with negligible resistance drift [1210.7933][0805.0917].

- **Device operation**: Pixel modules with 75 μm thin n-in-p sensors demonstrate raw hit efficiencies up to 98% at thresholds as low as 2.3 ke, with full charge collection attainable at moderate bias ($\sim$21 V pre-irradiation, $<$500 V post-irradiation) [1310.5854]. This performance is sustained throughout anticipated HL-LHC lifetimes.

## 6. Comparison to Conventional Bump-Bonding and Limitations

The table below summarizes the salient differences between SLID and standard bump-bonding technologies:

| Attribute           | SLID                             | Bump-Bonding                |
|---------------------|----------------------------------|-----------------------------|
| Formation Temp      | 240–320 °C (interdiffusion)      | 220 °C (reflow, Sn/Pb)      |
| Final Joint Tₘ      | >600 °C (Cu₃Sn)                  | ~220 °C (Sn/Pb eutectic)    |
| Pitch               | ≥20 μm (rectangular/litho pad)   | ≥25 μm (spherical bump)     |
| Stackability        | Multi-layer (no remelt)          | Single-layer (remelts)      |
| Shear Strength      | 25–40 MPa                        | 10–20 MPa                   |
| Radiation Tolerance | ≥$10^{16}$ n$_\mathrm{eq}$/cm²   | Sufficient, varies w/ alloy |
| Complexity          | Needs precise plating, alignment | Standard, reflow required   |

SLID is more robust against high-temperature post-processing and vertical stacking, supports finer interconnect pitches, and delivers superior mechanical strength and radiation tolerance [1109.3299][1310.5854][1202.6497][0805.0917]. However, it requires stringent control over surface preparation, plating uniformity, alignment (<10 μm achievable), and passivation opening reliability. Elevated bond temperatures limit some applications, and tight process integration is necessary to leverage its advantages.

## 7. Applications, Impact, and Future Directions

SLID has become a core technology for high-density, vertically integrated systems with extreme reliability demands, demonstrated by its adoption in radiation-hard pixel tracker modules at the ATLAS HL-LHC upgrade [1109.3299][1310.5854][1210.7933][1202.6497]. By enabling active area maximization (four-side buttable tiling), wafer-level throughput, and vertical integration (multi-layer stacking with ICVs/TSVs), it is suitable for advanced 3D-SoCs and hybrid sensor–ASIC technologies [0805.0917]. 

Ongoing process refinements target improvement in plating uniformity, self-alignment glues, and further scaling of pad pitch (potentially <10 μm), with increased automation in chip-to-wafer placement and BCB window opening quality. For future vertex detectors, enhancements in low-noise performance, stackable architectures, and manufacturability for large-area systems remain active areas of R&D [1310.5854]. 

A plausible implication is that with continued process control development, SLID combined with advanced vertical routing (ICVs/TSVs) could supplant bump-bonding for a wide class of high-density, high-reliability integration challenges across microelectronics and sensor domains.

Source: https://www.emergentmind.com/topics/solid-liquid-interdiffusion-slid