---
title: 'SINLK: Tree-Aware Data Placement for CXL-HM'
url: https://www.emergentmind.com/topics/sinlk
type: topic
---

# SINLK: Tree-Aware Data Placement for CXL-HM

SINLK is a **tree-structure aware, node-grained data placement scheme for tree-structure indexes on CXL-HM**, introduced for heterogeneous memory systems in which fast memory is CPU-attached DRAM and slow memory is CXL-attached memory [2507.18559]. It is designed for tree-structure indexes such as **B+ trees** and **radix trees / ART**, and is motivated by the mismatch between generic page-level placement schemes and the node- and path-centric access structure of trees. The paper argues that CXL memory should be treated neither as PM nor as RDMA-backed far memory nor as conventional NUMA remote memory, but as slower **cache-coherent, byte-addressable load/store memory in the same physical address space** as local DRAM. Within that setting, SINLK uses tree level, leaf hotness, and root-to-leaf path structure to decide allocation and migration, with the goal of improving throughput and reducing tail latency under constrained fast-memory budgets [2507.18559].

## 1. Problem setting and motivation

SINLK is formulated for **CXL-based heterogeneous memory (CXL-HM)**, where a machine exposes two tiers: **fast memory** and **slow memory**. In the evaluated system, fast memory is CPU-attached DRAM and slow memory is CXL-attached DRAM. The paper reports that on its CXL 1.1 platform, slow memory has about **~2× latency** and **~60% bandwidth** relative to fast memory, while still providing memory semantics rather than a message-based interface [2507.18559].

The problem addressed is the placement of **tree-structure indexes** on this two-tier memory hierarchy. Tree indexes are treated as a special case because their behavior is structurally different from generic page-managed data. Operations traverse a **root-to-leaf path**, upper levels are disproportionately hot, and the natural granularity of allocation and access is the **node** rather than the page. The paper states that with 50 million keys, the upper half of levels contains less than **1%** of nodes but sees average access frequencies about **three orders of magnitude higher** than the lower half. It also reports that directly placing about **75% of tree memory on CXL-attached memory** can cause around **~70% performance loss** [2507.18559].

Prior approaches are characterized as inadequate for this setting for different reasons. NUMA-aware indexes assume remote memory attached to processors and therefore do not transfer to CXL-attached memory with no local compute. RDMA-oriented designs such as SMART rely on local caches of internal nodes; on CXL-HM, the paper finds roughly **~50%** of SMART’s overhead comes from local-cache maintenance. PM-oriented tree designs are treated as overly specialized to PM asymmetries and too static for CXL-HM. Generic CXL-HM tiering systems such as **MEMTIS**, **TPP**, and **Caption** are described as page-grained and therefore mismatched to tree-node hotness. Even in the top **1% hottest pages**, the hottest node contributes **82%** of accesses for Masstree and **85%** for ART, while the upper quartile node access counts are only **16** and **4**, respectively [2507.18559].

## 2. Structural principles and placement model

The paper’s central insight is that **the placement of tree-structure indexes on CXL-HM should match the tree’s inherent characteristics with CXL-HM features** [2507.18559]. This yields two explicit principles.

The **layer principle** is to store **upper nodes in fast memory as many as possible**. Because upper nodes are both few and frequently traversed, they offer high leverage per byte of fast memory. The **path principle** is to identify **hot paths** and place them in fast memory as much as possible. Since each lookup or update follows a full root-to-leaf path, improving the residency of an entire hot path is more effective than promoting isolated nodes [2507.18559].

Operationally, SINLK is **tree-structure aware** because it makes placement decisions using tree semantics. Level is a first-class placement signal. The scheme enforces a **single-boundary structure**, meaning that if a node is in fast memory, its ancestors should also be in fast memory. This prevents fast-memory children from hanging below slow-memory parents and aligns placement with traversal paths [2507.18559].

SINLK is also **node-grained**. Each node may be allocated in fast or slow memory independently; migration queues hold nodes rather than pages; and hotness is tracked at the leaf level as a proxy for path hotness. The design depends on CXL’s unified address space and coherent load/store semantics, which allow the actual tree nodes to reside in either tier without an explicit remote-access protocol or software cache [2507.18559].

Initial placement is governed by the parameter \(L_{fast}\), the **highest level of fast-memory node allocation**. When a node is created, or when structural changes alter its position, the rule is: if the node level \(l < L_{fast}\) **and** the parent is in fast memory, allocate it in fast memory; otherwise allocate it in slow memory. This rule is the paper’s cheap allocation-time approximation of the layer principle and is also the mechanism that preserves the single-boundary structure [2507.18559].

## 3. Runtime mechanisms

SINLK is organized into a **frontend module** and a **background module** [2507.18559]. The frontend runs on the tree-operation critical path and is intentionally small. It performs **layer-aware allocation** and **leaf-centric access tracking**. The background module contains the **migration trigger**, **promotion executor**, **demotion executor**, **cooler**, and **watermark maintainer**, which carry out migration and parameter adjustment asynchronously [2507.18559].

A key design choice is **leaf-centric access tracking**. The paper states that tracking every node on every traversal causes **over 50% performance drop**, so SINLK tracks only **leaf access frequency**. The rationale is that every operation reaches a leaf, and a hot leaf identifies a hot root-to-leaf path. Each leaf therefore stores access-frequency metadata, and only the accessed leaf’s frequency is updated on the critical path [2507.18559].

Migration is explicitly **structure-aware**. If a **leaf in slow memory** is hot, promotion recursively brings the leaf and its **slow-memory ancestors** into fast memory, rapidly constructing a fast-memory hot path. Demotion is constrained to preserve the single-boundary structure. The demotion procedure stops if `cur.level < L_demote`, skips demoting an internal node if at least one child is still in fast memory, demotes the current node otherwise, and then enqueues the parent if needed. Here, \(L_{demote}\) is the **lowest level participating in demotion** [2507.18559].

Hot and cold nodes are identified with a **logarithmic histogram** of leaf access frequencies. Two threshold parameters, \(T_{hot}\) and \(T_{cold}\), are derived from control parameters \(P_{hot}\) and \(P_{cold}\). The paper defines \(T_{hot}\) as the value where nodes with frequency higher than \(T_{hot}\) **just exceeds** \(P_{hot}\), and \(T_{cold}\) as the value where nodes with frequency lower than \(T_{cold}\) **just falls below** \(P_{cold}\). The **cooler** periodically halves all leaf frequencies, and because the histogram is logarithmic this cooling can be implemented by shifting bins left by one position [2507.18559].

A further control mechanism is the **hyper watermark mechanism**, which jointly tunes \(L_{fast}\), \(P_{cold}\), \(P_{hot}\), and \(L_{demote}\) based on fast-memory usage. The paper sets **\(U_{high} = 95\%\)** and **\(U_{low} = 85\%\)**. When usage exceeds \(U_{high}\), SINLK reacts aggressively: it halts promotion, increases demotion likelihood by increasing \(P_{cold}\) and decreasing \(P_{hot}\), intensifies demotion by decreasing \(L_{demote}\), decreases \(L_{fast}\), wakes the trigger and demotion executor, and repeats until usage falls below \(U_{high}\). When usage falls below \(U_{low}\), it reacts conservatively by increasing \(P_{hot}\), \(L_{demote}\), and \(L_{fast}\), while decreasing \(P_{cold}\) [2507.18559].

| Parameter or mechanism | Role | Value or behavior |
|---|---|---|
| \(L_{fast}\) | Highest level of fast-memory allocation | Allocate in fast memory if \(l < L_{fast}\) and parent is in fast memory |
| \(L_{demote}\) | Lowest level participating in demotion | Demotion stops if `cur.level < L_demote` |
| \(T_{hot}\), \(T_{cold}\) | Hot/cold thresholds | Derived from histogram using \(P_{hot}\), \(P_{cold}\) |
| \(U_{high}\), \(U_{low}\) | Fast-memory usage watermarks | \(95\%\) and \(85\%\) |
| Cooler | Frequency aging | Periodically halves leaf access frequencies |

## 4. Integration with existing indexes

SINLK is presented as a **placement layer/framework** rather than as a new index structure [2507.18559]. The paper demonstrates integration with **Masstree** as a B+ tree variant and **ART** as a radix-tree implementation, denoted **S-Masstree** and **S-ART**. Most original index logic is preserved, including search, update logic, and existing structural operations. The required changes are concentrated in metadata, allocation hooks, tracking, migration interfaces, and migration-safe concurrency [2507.18559].

The metadata additions are small. Developers add **1 byte** in internal nodes for node level and memory type, and **2 bytes** in leaf nodes for access frequency. The measured overhead is **0.36% / 0.93%** for Masstree internal/leaf nodes and **0.04%–1.3% / 2.0%** for ART internal/leaf nodes. The framework implementation itself is reported as **~1.8k LOC** core framework, plus **~450 LOC** interfaces for Masstree and **~320 LOC** interfaces for ART [2507.18559].

The amount of required code modification inside the original tree implementations is limited. The paper reports about **~150 LOC** modified in a 25k LOC Masstree codebase and about **~50 LOC** modified in a 1.7k LOC ART codebase, both under **3%** of internal tree code. The paper characterizes this as allowing developers to adapt existing tree indexes to CXL-HM with low integration burden [2507.18559].

Concurrency during migration is handled explicitly. The migrating node and its parent are **locked** until migration completes to prevent concurrent writes. For reads, SINLK uses an **unused version bit** to indicate migration status, and correctness relies on **optimistic reads** that check versions before and after reading and retry on change. Shared SINLK state such as parameters and histogram is updated by background workers via atomic operations like **CAS**, and the paper states there is no lock contention between background workers [2507.18559].

## 5. Evaluation and reported performance

The evaluation is performed on a real CXL platform with an **Intel Xeon Platinum 8468V**, **48 cores**, **395 MiB CPU cache**, **32 GiB DRAM**, and **32 GiB CXL-attached DRAM**, with a single socket used to avoid confounding NUMA effects [2507.18559]. Most experiments use **28 threads**, with scalability additionally tested up to **48 threads**. Workloads include a **Skewed Partition (SP)** microbenchmark where **90% of requests target 5% of contiguous keys**, YCSB with **Zipfian** access, and two **Alibaba block traces** denoted **Trace A** and **Trace B** [2507.18559].

Baselines include Linux weighted interleave allocation, **TPP**, **MEMTIS**, **Caption**, and HM-optimized tree indexes such as **PAC-L** for ART and **Mass-L** for Masstree. The microbenchmark additionally includes **S-Prophet** as an idealized upper bound in which all hot paths are placed in fast memory at initialization [2507.18559].

The headline results reported in the abstract are **up to 71% throughput improvement** and **up to 81% P99 latency reduction** compared with state-of-the-art placement schemes such as MEMTIS and HM-optimized tree-structure indexes in YCSB and real-world workloads. The introduction further reports that on synthetic workloads SINLK achieves up to **133% higher throughput** and **67% lower P99 latency** than MEMTIS; on YCSB, up to **71%** higher throughput than MEMTIS and **60%** higher than optimized PACTree; and on real workloads, up to **66%** higher throughput and **81%** lower P99 latency than MEMTIS, and **44%** higher throughput and **63%** lower P99 latency than optimized PACTree [2507.18559].

The detailed workload results are consistent with the path-aware design. For the SP microbenchmark with Masstree, SINLK outperforms the baseline by **50%–82%** and approaches **S-Prophet** on the first three workloads. For macrobenchmarks, **S-ART** improves over the baseline by **32%–84%**, while **S-Masstree** improves by **31%–57%**, except for **Short Ranges**. In the Update Heavy microbenchmark with Masstree, average read and write latencies are both **under 1 μs**, and **P90 read latency** is **73% lower than the baseline** [2507.18559].

| Context | Comparator | Reported result |
|---|---|---|
| Abstract headline | State-of-the-art schemes and HM-optimized indexes | Up to **71% throughput improvement** and **81% P99 latency reduction** |
| Synthetic workloads | MEMTIS | Up to **133% higher throughput** and **67% lower P99 latency** |
| YCSB | MEMTIS / optimized PACTree | Up to **71%** higher throughput than MEMTIS and **60%** higher than optimized PACTree |
| Real workloads | MEMTIS / optimized PACTree | Up to **66%** higher throughput and **81%** lower P99 latency than MEMTIS; **44%** higher throughput and **63%** lower P99 latency than optimized PACTree |
| SP microbenchmark with Masstree | Baseline | **50%–82%** higher throughput |
| S-ART macrobenchmark | Baseline | **32%–84%** higher throughput |
| S-Masstree macrobenchmark | Baseline | **31%–57%** higher throughput except **Short Ranges** |

The paper also reports adaptation and overhead measurements. When the hot region shifts every **60 s**, SINLK experiences a temporary throughput dip but fully recovers within **up to 17 s**. Varying migration-trigger and cooler wake-up intervals across five configurations causes less than **5% deviation** from average performance. At **48 threads**, SINLK reaches **28.6×–38.1×** the throughput of a single thread. Background workers account for only **1.51‰–2.97‰** of total runtime [2507.18559].

An ablation-style factor analysis attributes the gains to several components. **Layer-aware allocation** alone yields **31.9%–49.8%** performance gain over baseline. Tracking only leaves costs **5.1%–7.0%** versus the previous step, whereas tracking all nodes causes about **60% degradation**. Adding migration improves performance by **2.8%–28.7%** over layering alone, and histogram-based dynamic thresholding adds another **1.7%–16.8%** over fixed thresholds [2507.18559].

## 6. Limitations, scope, and interpretation

SINLK is explicitly targeted at a **two-layer** memory hierarchy consisting of fast and slow memory [2507.18559]. The paper suggests that extension to multi-tier memory could be done by ordering tiers by latency and bandwidth and applying SINLK pairwise between adjacent tiers, but this is presented as future work rather than an implemented feature.

The paper also identifies a limitation of **leaf-centric tracking**. Because promotion starts from hot leaves, it may miss an internal node whose children are individually not hot enough but whose aggregate traffic is high; these are termed **false negative internal nodes**. The reported probability of such cases is less than **0.9%** under a standard Zipfian B+ tree workload with 20M keys, and the paper states they were observed only at the last internal level [2507.18559].

Workload dependence is another stated limitation. SINLK is most effective when access is skewed and hot paths matter. Its gains are weaker for **Short Ranges**, where scan performance depends heavily on how many **leaves** reside in fast memory. The paper also mainly focuses on tree indexes that **store values in leaves** and demonstrates integration only with Masstree and ART, although it intends the framework to be broader [2507.18559].

A broader significance of SINLK, as presented in the paper, is that it redefines what “native” optimization for CXL-HM means for tree indexes. It does not redesign trees as if CXL memory were PM, does not impose RDMA-style software caching, and does not rely on page-granularity migration. Instead, it aligns the unit of placement with the **node**, the dominant locality pattern with the **hot path**, and the static bias with **upper-level hotness**. This suggests a general systems principle for CXL-resident indexes: when memory semantics remain coherent and byte-addressable, structural placement policies can be more appropriate than page-oriented tiering for pointer-rich data structures [2507.18559].

Source: https://www.emergentmind.com/topics/sinlk