--- title: Simplified SSC Decoding url: https://www.emergentmind.com/topics/simplified-successive-cancellation-ssc-decoding type: topic --- # Simplified SSC Decoding Searching arXiv for the cited SSC and Fast-SSC papers to ground the article in the literature. Simplified successive-cancellation (SSC) decoding is a modification of successive-cancellation (SC) decoding for polar codes in which entire subtrees of the SC decoding tree are pruned whenever they correspond to constituent codes that can be decoded immediately, most fundamentally rate-0 and rate-1 subcodes. In the binary-input memoryless symmetric (BMS) setting, this pruning changes the latency law from the linear behavior of conventional SC to sublinear behavior under full parallelism, and to a resource-dependent law under constrained parallelism: for block length $N=2^n$, code rate $R$, scaling exponent $\mu$, and $P$ processing elements, the latency satisfies $O\!\left(N^{1-1/\mu}\right)$ in the fully-parallel regime and more generally $O\!\left(N^{1-1/\mu}+\frac{N}{P}\log_2\log_2\frac{N}{P}\right)$ under hardware resource constraints [1909.04892] [2012.13378]. In closely related literature, “fast-SSC” and fast SC decoders extend the same pruning principle to additional constituent-node classes such as repetition and single-parity-check nodes, sequence-based nodes, and non-binary special nodes [1504.06247] [2204.12115] [2401.07433]. ## 1. SC-tree formulation and the core SSC pruning rule SC decoding can be represented as a full binary tree of depth $n=\log_2 N$, with $N$ leaf nodes. At each node $v$, log-likelihood ratios (LLRs) $\alpha_v[i]$ propagate from parent to children, and hard decisions $\beta_v[i]$ propagate from children to parent. In the standard binary formulation, the left-child LLRs are computed by \[ \alpha_{\ell}[i] = f\bigl(\alpha_v[i],\alpha_v[i+N^m/2]\bigr) = \mathrm{sgn}\bigl(\alpha_v[i]\bigr)\,\mathrm{sgn}\bigl(\alpha_v[i+N^m/2]\bigr) \min\!\bigl(\lvert\alpha_v[i]\rvert,\lvert\alpha_v[i+N^m/2]\rvert\bigr), \] and, after decoding the left half, the right-child LLRs are computed by \[ \alpha_{r}[i] = g\bigl(\alpha_v[i+N^m/2],\alpha_v[i],\beta_\ell[i]\bigr) = (-1)^{\beta_\ell[i]}\,\alpha_v[i+N^m/2] + \alpha_v[i]. \] At a leaf corresponding to bit $u_i$, if the position is frozen then $\beta_v=0$; otherwise $\beta_v=0$ for $\alpha_v\ge 0$ and $\beta_v=1$ for $\alpha_v<0$ [1504.06247]. In the fully parallel time-step model used in the sublinear-latency analysis, standard SC visits the full tree, so its latency is proportional to the number of visited nodes or edges. The SC tree has $2N-1$ nodes, and standard SC therefore has latency $2N-1$ in that model; equivalently, standard SC traverses a full binary tree of depth $n$ and has latency proportional to the number of tree edges, namely $O(N)$ [1909.04892] [2012.13378]. SSC, in the sense analyzed by Alamdar-Yazdi and Kschischang and its later asymptotic study, prunes two special constituent nodes. A rate-0 node is a subtree whose leaves are all frozen, so the decoder immediately outputs all zeros. A rate-1 node is a subtree whose leaves are all information bits, so the decoder makes hard decisions in parallel directly from the input LLRs. Once such a node is identified at depth $s$, the entire subtree below it is decoded in one shot and is not recursively traversed further. The resulting reduction in the number of visited nodes is the fundamental mechanism behind SSC latency reduction [1909.04892] [2012.13378]. ## 2. From SSC to fast-SSC: richer constituent-node families Related fast-SSC literature enlarges the class of one-shot constituent decoders beyond rate-0 and rate-1. In addition to those two node types, a repetition (REP) node is a subtree in which only the last bit is information; its decision rule is based on the sign of the sum of all input LLRs, \[ S=\sum_{i=1}^{N}\alpha_v[i],\qquad b= \begin{cases} 0,&S\ge0,\\ 1,&S<0, \end{cases} \qquad \beta_v[i]=b\ \forall i. \] A single-parity-check (SPC) node is a subtree in which only the first bit is frozen; decoding proceeds by hard decisions $HD[i]=\mathbf1_{\{\alpha_v[i]<0\}}$, parity computation $\mathrm{parity}=\bigoplus_{i=1}^N HD[i]$, identification of the least-reliable index $j=\arg\min_i|\alpha_v[i]|$, and, if needed, flipping that least-reliable decision [1504.06247]. In the throughput-centric hardware formulation, the stated costs for these four fast constituent codes are: rate-0, 1 cycle; rate-1, 1 cycle; REP, $\log_2N$ cycles to sum via an adder tree; SPC, $\log_2N+1$ cycles for a comparator tree plus a final XOR [1504.06247]. In a separate FPGA-oriented time-step model with parallelism $P$, the approximate node costs are stated differently: $t_{\text{node}}(\text{rate0})=1$, $t_{\text{node}}(\text{rate1})=1$, $t_{\text{node}}(\text{REP})=1$, $t_{\text{node}}(\text{SPC})=2$, and $t_{\text{node}}(\text{generic length }M)=2\lceil M/P\rceil-1$ [2007.11394]. These differing figures reflect different hardware and scheduling assumptions rather than incompatible definitions. Fast-SSC is therefore best understood as a family of SSC-derived decoders in which the pruning criterion is broadened from pure rate-0/rate-1 recognition to a catalog of constituent subcodes with closed-form or small-block decoders. This broader viewpoint also underlies later sequence-node, generalized-parity, and non-binary constructions [2204.12115] [2401.07433]. ## 3. Asymptotic latency and scaling-law analysis For a BMS channel $W$, block length $N=2^n$, fixed error target $p_e\in(0,1)$, and any valid upper bound $\mu$ on the channel’s scaling exponent, the principal asymptotic result for SSC is \[ \mathcal{L}_{\mathrm{SSC}}(N)=O\!\bigl(N^{1-1/\mu}\bigr), \] establishing sublinear latency in the block length [1909.04892]. The scaling exponent $\mu$ captures the speed of polarization such that the gap to capacity $I(W)-R$ scales like $O(N^{-1/\mu})$; representative values stated in the literature are $\mu\approx 3.6$ for the binary erasure channel (BEC), $\mu\approx 4$ for AWGN, and more broadly $\mu\in[3.579,4.714]$ for typical BMS channels [2012.13378]. The proof strategy partitions the polarization process into rounds and uses two probabilistic ingredients. First, only a vanishing fraction of synthetic channels remain unpolarized: for the random Bhattacharyya process $Z_n$ of channel $W$, \[ \Pr\bigl(Z_n\in[2^{-\nu n},\,1-2^{-\nu n}]\bigr)\le c\,2^{-n/\mu} \] for fixed $\nu>1$. Second, sufficiently polarized parent channels generate subcodes that are entirely rate-0 or rate-1 and are therefore pruned. The combination implies that, except for $O(N^{1-1/\mu})$ subtrees, the decoding tree collapses into immediately decodable constituent nodes [1909.04892]. The numerical validation in that analysis reports tight agreement between the asymptotic exponent and simulated latency curves. When plotting $\log_2(\text{latency})$ versus $\log_2 N$ for BEC, BAWGNC, and BSC, SC exhibits slope approximately $1$, while SSC exhibits slope approximately $1-1/\mu$: for BEC, $\mu\approx 3.63$ gives slope approximately $0.72$; for BAWGNC, $\mu\approx 4$ gives slope approximately $0.75$; for BSC, $\mu\approx 4.2$ gives slope approximately $0.76$ [1909.04892]. The same study states that most of the latency reduction arises from the parallel decoding of subcodes of rate $0$ or $1$. ## 4. Parallelism, processing elements, and constrained-latency laws The fully-parallel asymptotic law does not by itself characterize practical decoder latency, because hardware typically provides only a limited number of processing elements (PEs). In the resource-constrained analysis, $P$ denotes the number of PEs available to compute SSC node operations in parallel, with $1\le P\le N/2$. The pruned SSC decoding tree is partitioned into a top region, comprising layers up to depth approximately $\log_2(N/P)$, and a bottom region, comprising the remaining $P$-rich layers. Each edge at depth $s$ is assigned weight $\lceil 2^s/P\rceil$, representing the number of time steps needed to process that edge with $P$ PEs [2012.13378]. This yields the general bound \[ L(N,P)=O\!\biggl(N^{1-1/\mu}+\frac{N}{P}\log_2\log_2\frac{N}{P}\biggr). \] The first term is the polarization latency, arising from decoding highly polarized subtrees in the bottom region. The second term is the serial-overhead term, arising because the top approximately $\log_2(N/P)$ layers cannot exploit full parallelism [2012.13378]. Three asymptotic corollaries organize the parallelism-versus-latency trade-off. In a fully-parallel implementation with $P=N/2$, the serial-overhead vanishes up to constants and the latency reduces to $O\!\left(N^{1-1/\mu}\right)$. In a fully-serial implementation with $P=1$, the latency specializes to \[ L=O\!\bigl(N^{1-1/\mu}+N\log_2\log_2N\bigr), \] with dominant term $N\log_2\log_2N$, and a refined analysis yields the exact prefactor \[ L=(2+o(1))\,N\log_2\log_2N. \] In a semi-parallel implementation, $P=N^{1/\mu}$ is the smallest number of PEs that asymptotically matches the fully-parallel latency order $O\!\left(N^{1-1/\mu}\right)$ [2012.13378]. Simulation results in the same analysis validate both the exponent and the threshold behavior. For fully serial decoding, plots of $L/N$ versus $\log_2\log_2N$ for BEC, BAWGN, and BSC are reported as straight lines of slope approximately $2$, confirming $L\approx 2N\log_2\log_2N$. For a BEC with $I(W)=0.5$ and $p_e=10^{-3}$, plots of $\log_2 L$ versus $\log_2 N$ for $P\in\{1,N^{1/8},N^{1/\mu},N^{1/2},N/2\}$ show slopes moving from approximately $1$ at $P=1$ down to $1-1/\mu\approx0.72$ for $P\ge N^{1/\mu}$. The reported practical implication is that SSC achieves sublinear latency in $N$ with moderate parallelism $P\gtrsim N^{1/\mu}$, and that under severe parallelism constraints $(P=1)$ it replaces $O(N\log N)$ latency with $O(N\log\log N)$ [2012.13378]. ## 5. Hardware realizations and throughput-centric design Hardware work on fast-SSC emphasizes that algorithmic pruning is only useful if supported by a scheduling plan and datapath that preserve throughput. A representative architecture uses a binary-tree of Processing Units (PUs), where every PU can perform the standard $f,g$ updates and also realize local fast-SSC operations under control signals. Because the same PU design supports both regular SC and all four fast node types, no separate specialized hardware is needed per rate. Pre-computation is used so that, in one cycle, each PU computes both $f(\cdot)$ and the two possible $g(\cdot)$ outputs; a multiplexer selects the correct result in the next cycle. The controller inspects the constituent-code type of the current node and branches either into a fast decode subroutine or into standard left-right recursion [1504.06247]. The same implementation describes a block-level architecture consisting of LLR memory, a processing-element tree, parity-transmit units, a partial-sum generator, and a control unit/FSM. The datapath uses channel-LLRs quantized to 4 bits and inner LLRs quantized to 5-bit two’s-complement with 0 fractional bits, denoted $(C,L,F)=(4,5,0)$. Only one tree is instantiated and time-multiplexed across the full $2N-1$ nodes. Resource sharing is central: the same PU cell handles $f$, $g$, SPC, REP, and regular SC, with control signals steering the datapath [1504.06247]. In 45 nm Nangate FreePDK, the stated synthesis results are: maximum clock frequency 1.04 GHz; silicon area 275,899 $\mu\text{m}^2$; latency 156 cycles and throughput 5.81 Gbps for the $(1024,870)$ polar code; latency 266 cycles and throughput 2.01 Gbps for the $(1024,512)$ polar code. Compared with a 2b-SC pre-computation decoder of latency $N-1=1023$ cycles, the design is reported to achieve at least 60% latency reduction for $N=1024$, and up to about 85% reduction at high rates [1504.06247]. A later FPGA implementation of an SR-node-based fast-SSC decoder introduces a dedicated SR module into the overall architecture, with instruction memory, controller, processing module, partial-sum network, and SR pipeline. For a length-1024 rate-1/2 polar code on an Altera Stratix IV FPGA, the implementation is reported to achieve a throughput of 505 Mbps, which is 17.9% higher than the previous work [2007.11394]. The same comparison states that, although the SR-FSSC design uses 222 clock steps rather than 214 for a prior Fast-SSC implementation, its critical path is shorter, so $f_{\max}$ increases by 10%, yielding the net throughput gain [2007.11394]. This emphasizes that SSC-family decoders are often evaluated simultaneously in terms of tree-pruning efficiency, cycle count, and clock frequency. ## 6. Generalizations: sequence nodes, SR nodes, and non-binary fast SC Subsequent research extends SSC-style pruning to special-node families that are not reducible to the original rate-0/rate-1 classification. One binary extension is the SR1/SPC sequence node, denoted $NS(p,q,L)$, in which the leftmost child at level $q$ is a generic source node and all right descendants at levels $r=q,\ldots,p-1$ are either rate-1 or SPC nodes. The node depth $d=p-q$ measures the degree of enclosed parallelism, and special cases include SR1, where all right descendants are rate-1, and SSPC, where all right descendants are SPC [2204.12115]. The decoding of SR1/SPC nodes is formulated through two families of parity constraints. Parallel parity constraints (P-PC) originate from the source node and impose \[ \bigoplus_{j=1}^{2^d}\beta_p^i[(j-1)2^q+k]=\beta_q^{L_q}[k],\qquad k=1,\ldots,2^q, \] while segmental parity constraints (S-PC) arise from the SPC descendants. The proposed generalized fast decoder is two-stage: Stage 1 corrects P-PCs by computing source-node LLRs, decoding the source, and running Wagner’s SPC decoder in parallel on the induced subcodes; Stage 2 checks S-PCs and, if necessary, performs a constrained bit-flipping correction. In the unlimited-resource model, the overall SR1/SPC decode time is $T=T_1+T_2\in[T_1,T_1+2]$ [2204.12115]. For $N=512$, $R=5/6$, and $E_b/N_0=4$ dB, the reported time-step counts are 88 for FSSC, 72 for HFSC2, and 32 for the proposed SN-FSC, corresponding to a 62.9% reduction versus FSSC and a 43.8% reduction versus HFSC2; the decoding performance is described as near-ML [2204.12115]. Another binary generalization is the sequence repetition (SR) node. An SR node, denoted $SR(v,\mathrm{SNT},r)$, is a subtree whose descendants are rate-0 or REP nodes except for one source node at level $r$, which may itself be rate-0, rate-1, EG-PC, or generic rate-$C$. Decoding proceeds by forming source-node LLRs for each feasible repetition sequence, decoding the source node under each pattern, selecting the sequence maximizing the reliability metric, and reconstructing the full output by repetition and XOR. The FPGA-oriented SR-FSSC formulation gives \[ T_{\mathrm{SRFSSC}}=T_{\mathrm{FSSC}}-\sum_{\mathrm{SR\ nodes}}(\text{savings})+\sum_{\mathrm{SR\ nodes}} t_{\mathrm{SRnode}}, \] with \[ t_{\mathrm{SRnode}}=1+\left\lceil \frac{2^rL}{P}\right\rceil +1+\left\lceil \frac{2^j}{P}\right\rceil \] for launch, LLR aggregation and source decoding, selection, and partial-sum update [2007.11394]. Non-binary polar codes constructed from $2\times2$ kernels admit an analogous fast SC methodology. In that setting, the decoding tree carries $q$-ary LLR vectors over $\mathrm{GF}(q)$, and special nodes include rate-0, rate-1, multiplicative repetition (M-REP), and multiplicative SPC (M-SPC), along with five intermediate types (Types I–V) and two general patterns, GM-REP and GM-PC. Fast decoding avoids traversing the full tree by using closed-form symbol-LLR sums, local SPC or repetition decoders, and, in a simplified structure, fixed early-stage kernel coefficients $\mu^{(\nu,s)}=\gamma^{(\nu,s)}=\delta^{(\nu,s)}=1$ for all $s