---
title: Silicon-on-Insulator Quantum Devices
url: https://www.emergentmind.com/topics/silicon-on-insulator-quantum-devices
type: topic
---

# Silicon-on-Insulator Quantum Devices

Silicon-on-insulator (SOI) quantum devices are a class of solid-state systems and integrated circuits in which quantum degrees of freedom—spin, charge, valley, or photonic—are confined, controlled, and measured within the silicon device layer of a silicon-on-insulator substrate. The SOI architecture, defined by a thin crystalline silicon layer on an insulating silicon dioxide (SiO₂) “buried oxide” (BOX) that is itself bonded to a handle wafer, provides electrical isolation, enhanced confinement potentials, and compatibility with deep sub-100 nm CMOS processing. SOI quantum devices span a range of platforms, including spin and charge qubits in electrostatically-defined quantum dots, single-donor qubits, color center emitters for quantum photonics, superconducting transmon-based qubits, and hybrid quantum-classical circuits with integrated cryogenic electronics. The principal advantages of SOI derive from process-level control, monolithic integration capability, reduced parasitic couplings, and scalable fabrication routes enabled by state-of-the-art industrial foundries.

## 1. Substrate Engineering and Material Platforms

SOI quantum devices leverage both standard and isotopically enriched silicon-on-insulator substrates, with the BOX layer (typically 20–145 nm) serving as an electrical and thermal isolation layer. Device silicon layers range from 7 nm (fully depleted FDSOI nodes) to >100 nm for hybrid architectures. Isotopic purification of the silicon layer to achieve $^{29}$Si (spinful isotope) concentrations below 1 ppm is achieved by high-fluence $^{28}$Si$^-$ ion implantation and solid-phase epitaxy (SPE) annealing, yielding quantum-grade $^{28}$SOI with $>$100 nm thickness, defect densities below 1/nm, and no observable threading dislocations or nanovoids after optimized processing (77 K implantation, 620°C/10 min SPE) [2504.03332]. This nucleates a “silicon spin vacuum,” essential for multi-second electron spin $T_2$ in donor and dot qubits [0906.1995]. Hybrid epitaxial SOI stacks (e.g., 150 nm $^{28}$Si grown above natural Si/BOX) combine interface noise suppression and nuclear spin purity. BOX thickness and composition directly affect quantum device performance, as thin BOX ($\sim$25 nm) in 22 nm FDSOI provides aggressive electrostatic control but must be optimized to prevent back-gate leakage [2412.08422, 2507.21306].

## 2. Quantum Dot and Spin Qubit Architectures

Gate-defined quantum dots fabricated on SOI platforms exploit sharply confined device layers (7–15 nm), high-κ/metal gate stacks, and advanced lithography (gate pitch < 70 nm) to form single- and double-dot structures for electron or hole qubit encoding [1912.09805, 1912.08313]. In fully depleted SOI (FDSOI), vertical and planar fields enable manipulation of quantum dot potentials and tunable tunnel barriers. Qubit implementations include:

- **Hole-spin qubits**: p-type nanowire or planar transistors confine single holes; qubit rotations exploit strong spin-orbit coupling and electric-dipole spin resonance (EDSR). Coherent Rabi oscillations with frequencies up to 70 MHz are achieved by microwave drive on the gate; $T_2^*$ can reach $\sim$100 ns in natural Si and is expected to increase to μs in $^{28}$Si [1912.09805, 1912.08313].
- **Electron-spin and valley qubits**: SOI nanowire dots exhibit controllable valley splitting $\Delta_v$, with bias-tunable anticrossings between spin-like and valley-like qubit states. All-electrical spin/valley switching schemes use back-gate voltage to alternate between protected storage and fast driven manipulation [1912.11403]. Rabi rates up to 80 MHz are simulated for modest RF drive.
- **Pauli spin blockade readout**: Robust (0,2)-(1,1) blockade is exploited in double-dot geometries, with singlet-triplet splittings of 0.3–1.3 meV and blockade regions sustained up to 6 T magnetic field. PSB-based readout allows sub-microsecond detection and is readily compatible with 300 mm CMOS FDSOI process flows [1606.05855].
- **Ambipolar SOI quantum dots**: Devices confining either electrons or holes in reconfigurable double-dot arrays permit side-by-side benchmarking of electron-spin (long $T_2^{\text{echo}}\approx 28$ ms in $^{28}$Si) and hole-spin (strongly electrically controlled but more susceptible to charge noise, $T_2^*\lesssim 1$ μs) qubits. Gate-based reflectometry affords integration times down to 100 ns for single-shot discrimination [2009.13944].
- **Isotopically enriched $^{28}$SOI FinFETs**: Donor qubits (e.g., $^{31}$P, $^{121}$Sb) embedded in quantum-grade $^{28}$Si films on SOI benefit from spectral diffusion suppression, with echo $T_2$ projected to tens or hundreds of seconds; transport signatures (Coulomb blockade, single-electron occupancy) are robust at $<1$ K [0906.1995].

## 3. Integrated Quantum Photonic and Color Center Devices

SOI is uniquely suited for heterogeneous quantum photonic integration due to its high-index-contrast waveguide properties and compatibility with standard photonic foundry processes.

- **Programmable TFM-encoded quantum state sources**: Photonic devices integrating an $N$-tap finite impulse response (FIR) spectral shaper and MZI-coupled ring resonators generate maximally entangled time-frequency mode (TFM) states in up to $D=4$ dimensions, with simulated state fidelities of $F_s=0.950$ (D=2), $0.954$ (D=3), $0.971$ (D=4). These sources implement high-dimensional entanglement with on-chip programmability in linear and nonlinear stages, leverage standard 220 nm/2 μm SOI stacks, and employ CMOS-compatible phase shifters [2504.09957].
- **Color centers as quantum emitters and spin-photon interfaces**: Controlled formation of W, G, I, T, C, M, and novel CN* centers is achieved via $^{12}$C and H co-implantation, followed by activation annealing (optimal windows: W—240°C, G—200°C, I—530°C, T—525°C, etc.). Some, e.g., T and M centers, offer optically active spins with coherence times $T_2\gtrsim 100$ μs. Formation dynamics and density are highly sensitive to anneal parameters and fabrication sequence, with remote O$_2$ plasma ashing minimizing post-anneal emitter loss [2601.17919]. 
- **Deterministic single-defect creation**: Femtosecond laser annealing enables deterministic, maskless creation of G and W centers in SOI at threshold fluence $F_{\mathrm{th}}\sim 330$ mJ/cm$^2$. Emitter lifetimes and ZPL linewidths are equivalent to ion-implanted standards; post-laser annealing selectively erases G centers while enhancing W emission [2304.03551].

## 4. Superconducting, Hybrid, and Monolithic Quantum-Classical Integration

- **Transmon qubits on SOI**: Fabrication of Al/AlO$_x$/Al Josephson junctions on SOI with undercut oxide (via anhydrous HF vapor etch) yields planar transmons with $T_1$ up to 3.5 μs and $T_2$ up to 2.2 μs. The process isolates the qubit island from lossy interfaces and is compatible with monolithic photonic and mechanical device integration. Comparable performance to sapphire- or bulk-Si-based transmons is established [1703.10195].
- **Hybrid quantum-CMOS circuits**: SOI FDSOI enables co-integration of quantum dots demonstrating Coulomb blockade and >600-transistor CMOS control logic (e.g., on-chip ring oscillators at GHz frequencies that function down to 4.2 K), paving the way for hybrid quantum-classical processing at deep cryogenic temperatures [1503.03993].
- **Monolithic multi-module assemblies**: Modular chiplet assemblies in 22-nm FDSOI CMOS integrate quantum dot arrays, SP8T cryogenic switches (IL < 1.1 dB, isolation >35 dB), and low-noise amplifiers (35 dB gain, $T_n = 4.2–6.2$ K over 709–827 MHz) for time-domain multiplexed readout. Fully monolithic architectures demonstrate charge sensitivity $t_1=70$ ns (SNR=1) and lay the foundation for scalable, all-silicon quantum processors [2405.04104].

## 5. Device Performance, Scaling, and Integration Metrics

SOI quantum devices exhibit:

- **Gate-defined QDs**: Charging energies $E_C=3–6$ meV (22 nm FDSOI), lever arms $\alpha=0.05–0.1$ eV/V, tunnel couplings $t_c$ tunable from <1 μeV to >10 μeV [2412.08422]. Coherence times—$T_2^*\approx 60$ ns (holes, natural Si), $T_2\approx$ multi-ms (electrons, $^{28}$Si), $T_1\gtrsim 10$ μs [1912.09805, 1912.11403].
- **Yield and Variability**: In single-hole transistor arrays (n=384 across 24x16 farm), gate length $PCL=28$ nm gives 30% good QD yield, dropping to <1% at $80$ nm; short-channel effects and DIBL increase for $PCL<40$ nm; machine-learning classifiers automate device selection [2507.21306].
- **Charge Noise**: 1/f-type spectra observed with $S_0\approx 6.5\,μ$eV$/\sqrt{\mathrm{Hz}}$ (median, holes, 22 nm FDSOI); best-in-class Si/SiGe or SiMOS ranges down to $0.1–4\,μ$eV$/\sqrt{\mathrm{Hz}}$ [2507.21306]. 
- **Quantum photonic sources**: TFM-entangled state generators achieve fidelities $>0.95$ for $D=2–4$ [2504.09957]; color centers support telecom emission (C centre at 1569.99 nm, 0.790 eV; T centre at 1325.40 nm, 0.935 eV) and can be integrated into photonic membranes and nanocavities [2601.17919].
- **Readout and I/O**: Dispersive gate reflectometry in ambipolar double dots achieves 100 ns integration times (SNR=1) [2009.13944], while RF-multiplexed readout modules support hierarchical scaling for $\gtrsim$100 qubit arrays [2405.04104].
- **Thermal Budget & Crosstalk**: SP8T switch insertion loss <1.1 dB, isolation >35 dB, LNA $T_n$ as low as 4.2 K at 650 MHz. System-level design accommodates cryo-operation with tight budgets for heat, interference, and I/O [2405.04104].

## 6. Challenges, Opportunities, and Roadmaps for Scaling

Key challenges in SOI quantum device scaling include minimization of charge noise (S$_0$ reduction by $\geq10\times$), control of process-induced variability (e.g., gate length, oxide thickness, interface roughness), mitigation of crosstalk via optimized routing/shielding, and heat management at sub-100 mK operation. Integration of error-correcting control firmware, local amplification/digitization, and 3D wiring leveraging the BOX for vertical vias are prominent engineering directions. Machine-learning–driven device classification and calibration are increasingly critical for high-yield arrays [2507.21306]. The combination of monolithic integration, standard foundry flows, and programmability in both quantum state construction and I/O paves the way for large-scale, all-silicon quantum processors supporting $\sim$1,000 or more spin qubits, high-dimensional quantum photonic states, and hybrid quantum-classical control [2507.21306, 2405.04104, 2504.09957].

_Table: Representative SOI Quantum Device Platforms and Metrics_

| Device type                | Physical basis / encoding         | Key metrics/figures       | Notable features                      |
|----------------------------|-----------------------------------|---------------------------|---------------------------------------|
| QD spin qubits             | Gate-confined e$^-$, h$^+$        | $T_2^*\sim$60 ns–ms, $\Omega_R$ up to 80 MHz | PSB readout, SOI nanowire scaling     |
| Donor spin qubits          | $^{31}$P, $^{121}$Sb in $^{28}$SOI| $T_2$(echo) $>$10 ms–1 s  | Single-ion detection, low noise       |
| TFM photonic sources       | TFM-encoded biphoton, ring array  | $F_s\approx 0.95–0.97$    | Programmable, scalable entanglement   |
| Color center emitters      | W, G, T, I etc.                   | ZPL: 970–1630 nm; $T_2>100$ μs | Spin-photon, telecom integration      |
| Superconducting transmon   | Al/AlO$_x$/Al JJ on SOI           | $T_1=3.5$ μs, $T_2=2.2$ μs| BOX undercut, planar integration      |
| Monolithic quantum-CMOS    | Quantum dot + cryo CMOS           | $\sim$1 GHz logic, $t_1=70$ ns readout | 22 nm FDSOI, multi-module systems     |

These platforms collectively offer an extensive and technically robust foundation for scalable quantum information processing, high-dimensional quantum photonics, and hybrid quantum–classical computing on silicon-on-insulator technology.

Source: https://www.emergentmind.com/topics/silicon-on-insulator-quantum-devices