--- title: 'QPU Slicing: Partitioning Quantum Workloads' url: https://www.emergentmind.com/topics/qpu-slicing type: topic --- # QPU Slicing: Partitioning Quantum Workloads Searching arXiv for recent papers on QPU slicing, multi-QPU partitioning, and circuit cutting. QPU slicing denotes a family of techniques for partitioning quantum computational resources so that a workload that would otherwise be executed monolithically is instead realized over smaller logical regions, separate QPUs, or cut subcircuits. Across the literature, the term covers at least three closely related practices: logically partitioning a single device into disjoint slices for concurrent programs, partitioning a circuit across multiple QPUs connected by remote operations, and cutting a circuit into hardware-sized fragments that are reassembled by classical post-processing [2601.08504] [2605.12583] [2205.05836]. The common objective is to reduce pressure on qubit count, connectivity, coherence, or initialization overhead while preserving either throughput, fidelity, or both. ## 1. Scope and meanings of QPU slicing A recurring source of ambiguity is that “QPU slicing” is not used uniformly. In neutral-atom multi-programming, slicing means a single chip is logically partitioned into independent “tiles” or “virtual zone layouts,” each hosting a separate circuit [2601.08504]. In cloud scheduling work, slicing means assigning disjoint subsets of physical qubits on one NISQ device to concurrent jobs, possibly with qubit-quality and crosstalk-aware placement [2411.05283]. In modular architectures, slicing means assigning logical qubits and remote gates across multiple QPUs connected by a communication fabric, with the partition evaluated against topology, ports, and congestion [2605.12583]. In circuit cutting, slicing means introducing cuts on wires or gates so that smaller subcircuits fit available QPUs and are later knitted together classically [2205.05836] [2207.00933] [2502.03445]. This suggests that the unifying concept is not a single mechanism but a single abstraction: a quantum computation is decomposed into resource-bounded slices whose coupling is either forbidden, mediated by remote operations, or reconstructed classically. The distinction matters. Some systems require semantic independence between slices, as in MultiQ’s checker for bundled neutral-atom programs [2601.08504]. Others allow explicit inter-slice communication, as in modular multi-QPU compilers and communication processors [2206.09938] [2509.02827]. Still others replace quantum coupling by classical recombination, as in CutQC and TensorQC [2205.05836] [2502.03445]. ## 2. Single-device slicing and multi-programming On a single physical QPU, slicing is most explicit in MultiQ’s neutral-atom architecture. MultiQ targets a zoned neutral-atom device with storage, entanglement, and measurement zones, and compiles each circuit not to physical coordinates but to a “virtual zone layout”: an abstract rectangular tile with storage and entanglement sub-zones, width, and height [2601.08504]. For a circuit with \(N_q\) qubits, storage rows \(N_r\), storage spacing \(S_s\), and a performance weight \(P_w\), layout width is chosen between the packing width \[ W_\text{min} = \left\lfloor \frac{N_q}{N_r} \right\rfloor \cdot S_s \] and a wider performance-oriented layout \[ W_\text{selected} = P_w \cdot W_\text{best} + (1 - P_w)\cdot W_\text{min}. \] The controller then bundles tiles into bins, places them on the 2D array, schedules movement and gate layers, and exploits “SIMD-like parallelization: a single hardware instruction can operate on qubits belonging to different, independent circuits” [2601.08504]. The neutral-atom hardware model constrains this slicing directly. MultiQ models a 280-qubit QPU with storage rows, SLM traps, AOD beams, a local blockade-mediated CZ via `@rydberg`, row-wise \(R_Z^R\), and global \(R_Y^G\), while also accounting for row-wise, diagonal, and column-wise AOD movement collisions [2601.08504]. Initialization and sorting take approximately \(82\,\mathrm{ms}\) per shot on a \(250\)–\(280\)-qubit device, whereas circuits up to \(170\) qubits have execution times shorter than initialization. This makes slicing primarily a throughput optimization: multiple small circuits can amortize one initialization. QSRA studies the same idea in a cloud NISQ setting. Jobs are tuples \((n_i,s_i,t_i)\), with \(n_i\) required qubits, \(s_i\) shots, and \(t_i\) submission time, and service time \[ t_E = s_i t_e. \] Its scheduler uses qubit-aware metrics such as \[ \eta = \frac{n_i}{N}, \qquad \text{size}_i = \eta t_\text{ser}, \] and a QHRRF priority \[ t_\text{qres} = \frac{t_\text{wait} + \eta t_\text{ser}}{t_\text{ser}}, \] then allocates connected qubit regions using the connectivity ratio \(r_i/r_a\) and the qubit-quality score \[ E_Q = \bigl(1 - \exp(t_e / T_Q)\bigr) E_\text{meas}. \] QSRA also merges nearby programs with similar \(t_e\) so that crosstalk-aware scheduling can be applied to the merged program rather than enforced via idle spatial buffers [2411.05283]. ## 3. Modular multi-QPU slicing When slices span multiple QPUs, the main issue becomes not initialization amortization but communication structure. QuPort formalizes this with three graphs: a weighted logical interaction graph \(G_L\), a directed physical coupling map inside each QPU, and an undirected QPU-level interconnect graph \(G_Q\) [2605.12583]. A partition \(\pi:Q_L\to V_Q\) induces cross-QPU traffic, boundary qubits, and link load, and TPCCAP optimizes \[ J(\pi) = \alpha \sum_{(i,j)\in E_L,\ \pi(i)\neq\pi(j)} w_{ij} d(\pi(i),\pi(j)) +\beta \sum_{q\in V_Q} \max(0,b_q-P)^2 +\eta \sum_{e\in E_Q} L_e^2. \] The first term penalizes weighted cut distance, the second communication-port overflow, and the third routed link-load congestion. This makes slicing explicitly topology-, port-, and congestion-aware rather than purely cut-minimizing [2605.12583]. A related line of work treats inter-QPU cost through graph cuts and temporal locality. “Quantum circuit optimization for multiple QPUs using local structure” models the circuit as a coupling graph with Laplacian \(\mathcal{L}_\mathrm{circ}\), then minimizes \[ C_{\text{KL}} = \sum_{j=1}^k \vec{v}_j^{T}\mathcal{L}_{\mathrm{circ}}\vec{v}_j \] under cardinality constraints for QPU size [2206.09938]. It supplements this with rolling time windows, so the effective partition can change over time when local interaction structure changes. The same work derives a remote CNOT from a shared Bell pair, local CNOTs, Hadamards, measurements, and classical communication, making explicit why inter-QPU gates are the costly resource [2206.09938]. LarQucut treats distributed slicing as a joint cutting-and-mapping problem. It allows both wire cuts and gate cuts, with classical post-processing and sampling costs \[ C_{\text{post}} = 4^{k_1}6^{k_2}, \qquad C_{\text{sample}} = 16^{k_1}9^{k_2}, \] then introduces “hemicut” pruning: after finding a full partition, it retains only “critical cuts” that substantially reduce remote gates [2502.21000]. It also identifies isomorphic subcircuits for result reuse and uses hotness- and weakness-aware placement to reduce SWAPs and EPR usage. At the architectural level, QNPU separates local computation from network communication. Each node contains a QPU for local gates and a QNPU for communication qubits, EPR management, and distributed protocols expressed in DistQASM via operations such as `teleport`, `cat_ent`, and `cat_disent` [2509.02827]. High-level instructions such as `SEND_TP_QUBIT` and `GET_TP_QUBIT` are implemented by micro-operations for EPR reservation, classical messaging, and quantum corrections, providing an execution substrate for fine-grained multi-QPU slicing [2509.02827]. ## 4. Circuit cutting and hybrid slicing Circuit cutting treats slicing as decomposition of one logical circuit into hardware-sized subcircuits whose joint behavior is reconstructed classically. CutQC performs vertical cuts on qubit wires and reconstructs the full output distribution through a Pauli-basis expansion: \[ P = \sum_{k=1}^{4^K} \bigotimes_{i=1}^{n_C} p_{i,k}. \] It uses a MIP cut searcher with objective \[ L \equiv 4^K \sum_{c=2}^{n_C} \prod_{i=1}^{c} 2^{n_i}, \] thereby making the post-processing blow-up from the number of cuts explicit [2205.05836]. CutQC supports full-definition reconstruction of the entire \(2^n\)-dimensional output vector and dynamic-definition reconstruction that recursively refines only selected bins, which is how it reaches 100-qubit-scale studies [2205.05836]. ScaleQC pursues the same hybrid objective but focuses on larger-than-QPU workloads. It uses a MIP-based DAG partitioner with load factor \(\alpha\), minimizes the maximum compute-graph degree \(L=\max_c(I_c+O_c)\), and adds “states merging” so that only coarse-grained bins of the output space are reconstructed at each recursion [2207.00933]. This allows benchmarks up to 1000 qubits and shifts the target from full-state reconstruction to locating high-probability solution states. TensorQC replaces naive classical reconstruction by tensor-network contraction, giving an upper bound \[ \mathcal{O}\!\left(4^{K_{\max}} m\right) \] instead of \(\mathcal{O}\!\left(4^{|E|} m\right)\), and adds Heavy State Selection so that only heavy outputs are retained in the reconstruction pipeline [2502.03445]. It reports execution of six realistic benchmarks up to 200 qubits using QPUs available nowadays and a single GPU, while reducing QPU size and quality requirements by more than \(10\times\) over purely quantum platforms [2502.03445]. shardQ specializes circuit cutting to encoder circuits and non-all-to-all superconducting hardware. It uses SparseCut, MPS compilation, and global knitting, and cuts CX gates via a Pauli-basis/QPD decomposition such as \[ {\rm CX}_{c\to t} =\frac12\Bigl( I_c\!\otimes\!I_t + Z_c\!\otimes\!I_t + I_c\!\otimes\!X_t - Z_c\!\otimes\!X_t \Bigr), \] then reconstructs target observables from global correlations rather than only local estimators [2511.05492]. This is a slicing strategy tuned to structured tensor encoders rather than general-purpose circuit graphs. ## 5. Algorithm-specific slicing and communication bounds Some slicing schemes are algorithm-structured rather than compiler-structured. In “Parallel circuit implementation of variational quantum algorithms,” slicing is obtained by removing coupling terms \(H_{\tilde C}\) from the quantum Hamiltonian so that \[ H - H_{\tilde C} = \sum_s H^{(s)}, \] with each \(H^{(s)}\) acting on a disjoint register [2304.03037]. The resulting pQAOA, pVQE, and pQA circuits run on smaller slices, while the removed couplings are evaluated classically in the objective. In symmetric cases, the same work states that “it is also possible to run full VQA models while training parameters using only one slice” [2304.03037]. This suggests that for some optimization encodings, slicing is not merely a hardware workaround but a statement about redundancy in the circuit representation. Hybrid annealing provides another algorithm-specific version. For larger-than-QPU lattice-structured Ising problems, the global Hamiltonian \[ H(x)=\sum_{i