---
title: Passive Matrix Addressing in Memory Crossbars
url: https://www.emergentmind.com/topics/passive-matrix-addressing
type: topic
---

# Passive Matrix Addressing in Memory Crossbars

Passive matrix addressing is a scheme employed in high-density device arrays—such as memristive and phase-change memory crossbars—to enable the electrical selection, readout, and programming of individual cells without the presence of per-cell active elements like select transistors. This approach is foundational to “1D1R” (one-diode–one-resistor) and “1R” (resistive only) architectures, achieving maximal density by crossing vertical and horizontal lines with only passive, two-terminal junctions at each intersection. While passive matrix addressing offers scaling benefits critical for neuromorphic computing and analog memory, it is fundamentally limited by sneak-path currents, nonlinear device physics, voltage-drop imbalances, and device variability, all of which impose distinct challenges and define the operational regime and achievable fidelity of such arrays [1910.05836][1906.12045].

## 1. Crossbar Array Architecture and Passive Addressing Protocols

A passive crossbar array forms the basis for this addressing technique: $m$ word lines (WLs) intersect $n$ bit lines (BLs), with each crosspoint containing a memory cell. In 1D1R and 1R arrays, these are realized by memristors (or phase-change resistors), with optional series diodes to enhance nonlinearity and block undesired leakage. No select transistor is present per cell, increasing spatial density and enabling integration of $>10^4$ cells per array [1910.05836][1906.12045].

To target a single cell $(p, q)$ during read or program, external drivers impose a selective voltage protocol. The classical “V/2” scheme assigns:
- $WL_p = +V_{sel}$, $BL_q = 0$
- all other $WL_{i\neq p} = +V_{sel}/2$, all other $BL_{j\neq q} = +V_{sel}/2$

This constrains the target device to experience $\pm V_{sel}$, half-selected devices $\pm V_{sel}/2$, and unselected devices ideally near zero net voltage. More advanced “V/3” protocols further distribute line potentials, reducing effective sneak-path contributions [1906.12045].

## 2. Device and Array-Level Electrical Behavior

Memristor devices in passive arrays exhibit non-ideal, nonlinear current–voltage (I–V) relations, further complicated by threshold switching. At small read biases (e.g., $V_r = 0.25\,$V), individual cells respond as $I(V) \approx G V$ with dynamic range $G_{on}/G_{off} \approx 50\,\mu$A$/2\,$pA [1906.12045]. Higher biases reveal nonlinearity, quantified by $\eta(V) = \tfrac{1}{2} [I(V)/I(V/2)] \approx 1.1\textrm{--}1.3$. Programming exploits this nonlinearity with pulses exceeding stochastic thresholds, typically $V_{th}^{set} \sim \mathcal{N}(1.19\,\textrm{V},\,0.31\,\textrm{V})$, $V_{th}^{reset} \sim \mathcal{N}(-1.39\,\textrm{V},\,0.37\,\textrm{V})$ [1906.12045].

At the array level, Kirchhoff’s laws are used to model static DC operation. Each current path is decomposed as $I_{cell}(i, j) = g_{cell}(i, j)\,[V_{WL}(i, j) - V_{BL}(i, j)]$, where $g_{cell}$ is the small-signal conductance. This results in a block-sparse matrix equation,
$$
G \mathbf{V} = \mathbf{I}_{app}
$$
jointly encoding all node voltages, conductances, line resistances, and imposed boundary currents. The nonlinear diode selector, if present, requires each $I_{cell}(V_C)$ to satisfy a transcendental equation involving the Lambert-W function:
$$
I_{cell}(V_C) = \frac{n V_T}{R} W\left( \frac{R I_S}{n V_T} e^{V_C/(n V_T)} \right)
$$
with $I_S$ the reverse saturation current, $n$ the ideality factor, $V_T$ the thermal voltage, and $R$ the resistance [1910.05836].

## 3. Sneak-Path Currents and Mitigation

Passive matrix arrays are fundamentally limited by sneak paths—unintended conductive routes through half-selected or unselected devices—which contribute parasitic current, obscure readout, and cause unintentional programming. For V/2 biasing, the measurable current for a selected cell is:
$$
I_p = G_{pq} V_{sel} + \sum_{i \neq p} G_{iq} \frac{V_{sel}}{2} + \sum_{j \neq q} G_{pj} \frac{V_{sel}}{2}
$$
If nearly all half-selected conductances are $G_{off}$ and the array dimension is $N$, the sneak contribution,
$$
I_{sneak} \approx (N-1) G_{off} V_{sel}
$$
becomes non-trivial for large $N$ or low $G_{off}$, limiting achievable selectivity [1906.12045].

Sneak-path mitigation employs advanced biasing:
- **V/2 scheme:** Reduces off-target voltages to half the selection voltage, scaling parasitic current as $G_{off} (V_{sel}/2)$.
- **V/3 scheme:** Distributes potentials so half-selected and unselected devices experience even lower biases, cutting sneak current by a further $2/3$ relative to V/2 [1910.05836][1906.12045].
- **Nonlinear selectors:** Use of 1D1R stacks, where diode-like selector nonlinearity ensures exponentially lower conductance at non-selected biases.

## 4. Device Variability, Error Propagation, and Addressing Accuracy

Device-to-device variability, especially in switching thresholds ($CV_{set} \approx 26\%$, $CV_{reset} \approx 27\%$ in $64\times64$ arrays) and conductance response, impacts both programmability and read reliability. The stochastic distribution of $V_{th}$ affects the probability that any given programming pulse yields the desired conductance increment, modelled as
$$
P(|V_w| \geq V_{th}) \approx 1 - \Phi\left( \frac{|V_w| - \mu_{th}}{\sigma_{th}} \right)
$$
where $\Phi$ is the cumulative normal distribution [1906.12045].

For analog-grade applications, tuning algorithms implement incremental write-verify cycles, each pulse followed by a conductance readout, using feedback to bring post-pulse deviation below preset windows (e.g., $|\epsilon| \leq 5\%$). Empirically, $>98\%$ of devices in a $4$k device array converge within $4\%$ absolute error after three programming cycles, despite threshold fluctuations [1906.12045].

## 5. Scalability, Line Resistance, and Biasing Strategies

The limits of passive matrix addressing are inevitably set by array size, line resistance, and biasing symmetry:
- **Line resistance ($R_{line}$):** Increasing $R_{line}$ (e.g., from $1\,\Omega$ to $20\,\Omega$ per line segment in a $100\times100$ array) causes voltage nonuniformity, raises effective $R_{select}$ for ON states, and lowers the sense margin ($\Delta V$) [1910.05836].
- **Array size:** Scaling from $10\times10$ to $200\times200$ exponentially increases numbers of half-selected paths and reduces the margin between ON/OFF states, with sense margin falling by an order [1910.05836].
- **Sense resistor ($R_{sens}$):** Optimal $R_{sens} \sim 0.5-1 \times R_{low}$ balances signal amplitude and Johnson–Nyquist noise [1910.05836].
- **Biasing:** Single-edge drive leads to highly uneven current distribution, whereas dual-side biasing and grounding flatten currents, equalizing cell heating and minimizing voltage offsets across the array [1910.05836].

Simulation-based guidelines suggest maintaining $R_{line} \ll R_{low}$, using V/3 biasing, optimizing selector parameters ($I_{S}\approx 10^{-12}$A, $n\approx1.5$), and employing dual-end biasing to ensure scalability beyond $10^6$ devices without catastrophic sense margin loss [1910.05836].

## 6. Programming Algorithms, Neuromorphic Applications, and Measured Performance

The efficacy of passive matrix addressing underlies applications such as analog neuromorphic computing. Using incremental-step write-verify routines, the $64\times64$ “4K-Memristor Analog-Grade Passive Crossbar Circuit” was programmed to grayscale levels $G \in[10,100]\,\mu$S at $0.25$V, with $98\%$ of devices within $\pm5\%$ of target value after three tuning cycles [1906.12045]. Multi-cycle re-tuning mitigates half-select drift.

As a demonstration, the array directly realized a single-layer perceptron for MNIST digit classification. Input voltages (downsampled pixels) were mapped to array columns; pre-trained weights were imported as cell conductances. Classification accuracy of $83.5\%$ (hardware, $1.8\%$ below software) was achieved with $1\%$ tuning error, confirming that V/2 addressing, multi-pass tuning, and careful biasing robustly support inference in practical tasks. Performance degrades gracefully as weight import error rises, sustaining operation even at $50\%$ perturbation with only minor accuracy drop [1906.12045].

## 7. Summary of Key Equations, Concepts, and Design Guidelines

Passive matrix addressing in high-density resistive memory crossbars is governed by a set of core equations and operational guidelines:

| Equation / Concept                | Expression / Range                                                        |
| ---------------------------------- | --------------------------------------------------------------------------|
| Cell current (Lambert-W form)      | $I_{cell}(V_C) = \frac{n V_T}{R} W\left( \frac{R I_S}{n V_T} e^{V_C/(n V_T)} \right)$ |
| Sneak-path current, V/2 scheme     | $I_{sneak} \approx (N-1) G_{off} V_{sel}$                                 |
| Sense margin                       | $\Delta V = V_{out}^{ON} - V_{out}^{OFF}$; $Margin(\%) = (\Delta V/V_{read})\times 100\%$ |
| Optimal selector parameters        | $I_S \approx 10^{-12}$A, $n \approx 1.5$ (for V/3 biasing)                |
| Tuning error (empirical)           | $\epsilon_{avg} < 4\%$ after 3 cycles in $4$k devices                     |
| Array scaling (reported)           | >$10^4$–$10^6$ devices possible with proper line resistance control        |

Design optimization relies on combining advanced biasing (e.g., V/3), selector nonlinearity, minimized line resistance, symmetric drive schemes, and iterative, feedback-based programming. These techniques support robust, analog-grade operation even in the presence of material and device-level stochasticity, confirming the viability of passive matrix addressing for next-generation neuromorphic and memory devices [1910.05836][1906.12045].

Source: https://www.emergentmind.com/topics/passive-matrix-addressing