---
title: Panel-Scale Reconfigurable Photonic Interconnects
url: https://www.emergentmind.com/topics/panel-scale-reconfigurable-photonic-interconnects
type: topic
---

# Panel-Scale Reconfigurable Photonic Interconnects

Searching arXiv for the cited work and closely related papers on programmable and panel-scale photonic interconnects.
Panel-scale reconfigurable photonic interconnects are large-area optical communication fabrics in which optical paths are altered by programmable switch nodes, tunable couplers, or nonvolatile photonic gates to connect chiplets, accelerators, or servers across a shared substrate or tiled assembly. Across recent work, the term encompasses glass-substrate photonic interposers up to \(500\text{-mm}\times500\text{-mm}\) or larger, panels of \(N\) accelerators that share a reconfigurable photonic fabric as one scale-up domain, and silicon-photonic programmable meshes whose projected panel-scale footprint includes a \(100\,\text{mm}\times100\,\text{mm}\) patch with \(\approx25\,000\) gates [2508.06079] [2510.08072] [2506.18592].

## 1. Architectural forms and network organization

Several distinct architectural families recur in the literature. One is the planar crossbar on a glass substrate, implemented as a two-layer waveguide fabric with a horizontal layer \(H\) and a vertical layer \(V\), where each \(H\)–\(V\) crossing contains a vertically-coupled add-drop racetrack resonator pair that functions as a \(2\times2\) optical switch node. In that formulation, the number of switch nodes is
$$
M = N_h \times N_v,
$$
and a multilayer extension uses
$$
M_{\text{total}} = \left(\sum_{i=1}^{L_h} N_{wg,hi}\right)\cdot\left(\sum_{j=1}^{L_v} N_{wg,vj}\right).
$$
This architecture is explicitly presented as panel-edge-to-panel-edge routing on a glass photonic interposer without active repeaters, while remaining compatible with commercial processor chiplets and \(3\text{D}\) HBM stacks [2508.06079].

A second family is the programmable silicon-photonic mesh. In "NEO-PGA: Nonvolatile electro-optically programmable gate array" [2506.18592], the basic unit cell is an MZI gate composed of two \(50{:}50\) MMIs and two Sb\(_2\)Se\(_3\)-clad arms on silicon waveguides. Two mesh organizations are distinguished. The circulating rectangular mesh functions as an optical circuit switch and can be reconfigured into ring resonators, dual-ring systems, and coupled-cavity arrays. The forward-only Clement-style mesh functions as a self-configurable PIC that progressively learns to sort two orthogonal beams.

A third family uses discrete switching stages. The \(64\times64\) Benes network based on \(2\times2\) split waveguide crossing MEMS switches contains \(2\log_2N-1=11\) stages for \(N=64\), with \(32\) switch cells per stage and \(352\) total cells [2305.17366]. Earlier work on microring switching organized an \(8\times8\) fabric from \(1\)-to-\(8\) demultiplexers and \(8\)-to-\(1\) multiplexers, enforcing path-independent insertion loss by a fixed demux-to-mux connectivity rule [1512.09323].

These architectures differ in switching physics, loss accumulation, and control strategy, but they share a common systems role: they create reconfigurable optical connectivity that can either emulate direct matchings for collective communication or implement fixed-depth routing fabrics with large port count.

## 2. Switching primitives, materials, and physical operating principles

The physical switch primitive strongly determines static power, reconfiguration speed, bandwidth, and layout density. In the NEO-PGA platform, the phase-change section is \(\sim10\,\text{nm}\) Sb\(_2\)Se\(_3\) on a \(400\,\text{nm}\) wide \(\times 65\,\mu\text{m}\) long Si ridge, capped by \(40\,\text{nm}\) Al\(_2\)O\(_3\), and driven by a PIN-diode microheater located \(\sim500\,\text{nm}\) from the waveguide with zero static loss. Sb\(_2\)Se\(_3\) is described as a wide-bandgap phase-change material with amorphous \(n\approx2.9\), \(k\ll10^{-3}\), and crystalline \(n\approx3.0\), \(k\approx10^{-3}\), giving \(\alpha_{\text{PCM}}\approx0.03\,\text{dB}/\pi\). The induced phase shift follows
$$
\Delta\phi(\lambda)= (2\pi/\lambda)\cdot\Delta n_{\text{eff}}\cdot L_{\text{PCM}},
$$
and the MZI splitting ratio is controlled by
$$
\kappa=\cos^2(\Delta\phi/2).
$$
The same work reports MZI insertion loss \(<0.5\,\text{dB}\) total and extinction ratio up to \(21\,\text{dB}\) [2506.18592].

The glass-panel crossbar instead uses thermally tuned resonant switch nodes. Each vertically-coupled add-drop racetrack resonator can be set to “pass-through” or “turn,” with \(\approx0.25\,\text{dB}\) bypass loss, \(0.5\,\text{dB}\) turn loss, and off-state extinction \(>15\,\text{dB}\). The path loss model is
$$
L_{\text{total}}(\lambda)=\alpha(\lambda)\cdot D + N_b\cdot L_{\text{bypass}}(\lambda)+N_t\cdot L_{\text{turn}}(\lambda)+2\cdot L_{ec}(\lambda),
$$
and for the stated worst-case \(500\,\text{mm}\) edge-to-edge route in an \(8\times8\) array of unit-interposers the estimate is \(23\,\text{dB}\) [2508.06079].

Microring-based switching provides another resonant mechanism. In the \(8\times8\) silicon photonic switch fabric, a change in applied voltage produces a temperature shift and a resonance displacement
$$
\Delta\lambda = \alpha\cdot\Delta T,
$$
with \(\alpha\approx0.11\,\text{nm/K}\), and \(4.2\,\text{V}\) across the heater shifts the ring by one free spectral range of \(\simeq13.2\,\text{nm}\). Through-port and drop-port transmission are modeled in terms of round-trip attenuation \(a\) and self-coupling \(t\), with extracted values \(a=0.99\) and \(t\approx0.95-0.98\) [1512.09323].

The MEMS split-waveguide-crossing switch is nonresonant and mechanically reconfigures the crossing geometry. Its OFF state is represented by
$$
R_{\text{off}}=
\begin{pmatrix}
0 & r\\
r & 0
\end{pmatrix},
$$
and its ON state by
$$
T_{\text{on}}=
\begin{pmatrix}
t & 0\\
0 & t
\end{pmatrix},
$$
with \(t\approx0.9-0.97\) and residual bar-coupling \(r_{\text{on}}<-22\,\text{dB}\). The switch region is \(23\times23\,\mu\text{m}^2\), the total device footprint is \(\simeq95\times100\,\mu\text{m}^2\), and the measured bandwidth spans \(1420\text{–}1600\,\text{nm}\) [2305.17366].

Taken together, these platforms illustrate the principal design trade-off. Volatile thermo-optic tuning is mature but incurs static power and thermal-management overheads. Nonvolatile phase-change meshes target \(P_{\text{static}}\approx0\,\text{W}\). MEMS switches target sub-\(\mu\text{W}\) average power and ultrawide optical bandwidth. Resonant glass-panel crossbars emphasize very large-area reach and WDM density.

## 3. Programming, calibration, and control planes

Programming methods range from analog, closed-loop multibit tuning to binary switching and topology-level scheduling. The NEO-PGA platform uses a closed-loop “program-and-verify” method with bidirectional, progressive tuning by partial amorphization and crystallization. After each pulse, a monitor reads output power and adjusts the next pulse amplitude until the target is within \(0.1\%\). Typical pulse conditions are \(V_a\approx7.5\text{–}9\,\text{V}\), \(\tau_a\approx400\,\text{ns}\) for amorphization and \(V_c\approx2.5\text{–}3.5\,\text{V}\), \(\tau_c\approx5\text{–}10\,\text{ms}\) for crystallization, with programming energy \(\lesssim20\,\text{nJ}\) for amorphization and \(o(100\,\text{nJ})\) for crystallization. Because the PCM is nonvolatile, the mesh is explicitly described as “set-and-forget,” and adjacent gates remain undisturbed with localized switching to \(\lesssim1\,\mu\text{m}\) [2506.18592].

The forward-only NEO-PGA mesh also introduces a self-configurable mode. In that case, a two-stage MZI network progressively tunes itself to route two orthogonal input vectors \(x,x'\) to outputs \(O_1,O_2\). This is not merely static circuit programming; it is a local closed-loop adaptation procedure embedded in the photonic fabric itself [2506.18592].

Microring fabrics use firmware-controlled heater biasing. The \(8\times8\) switch employs a Stratix V FPGA with DAC controllers, an embedded NIOS microprocessor, and an RTL scheduler that sequences ring bias updates to achieve simultaneous multi-ring tuning. The stated path-setup flow consists of request receipt, ring-index lookup, DAC writes, thermal settling over roughly \(1\text{–}10\,\mu\text{s}\), optional monitor-photodiode verification, and routing-table update. Demonstrated path-to-path reconfiguration used hold times of \(150\,\mu\text{s}\) and \(75\,\mu\text{s}\), with total cycle \(\lesssim350\,\mu\text{s}\) [1512.09323].

MEMS Benes fabrics require high-voltage actuation and pad-count reduction. The proposed control path is FPGA \(\rightarrow\) level-shifter array \(\rightarrow\) HV comb-drive drivers \((<30\,\text{V})\) \(\rightarrow\) comb electrodes, with direct row/column addressing used to avoid conventional \(N^2\) pads. Calibration provisions include built-in monitor photodiodes, automated OSA sweeps per die, and digital binary ON/OFF thresholds [2305.17366].

At the panel and scale-up-domain level, the control plane becomes a synchronization problem. One proposal assumes a lightweight control plane that synchronizes barrier and reconfiguration across a shared-memory domain, while the theory of adaptive photonic scale-up domains makes reconfiguration itself a schedule decision variable rather than a fixed overhead [2510.08072].

## 4. Communication-theoretic models and the reconfiguration decision

A central question is whether a reconfigurable photonic fabric should actually be reconfigured for a given communication step. In adaptive photonic scale-up domains, the system model uses \(n\) endpoints, link bandwidth \(b\), reconfiguration delay \(\alpha_r\), and a base topology \(G\). A collective is written as a sequence of matchings \(\mathcal{M}_i\) with volumes \(m_i\), and the aggregate demand matrix is
$$
\mathcal{M}=\sum_{i=1}^s m_i\,\mathcal{M}_i.
$$
Per-step completion time is
$$
DCT_i=\alpha+\delta\,\ell_i+\beta\,m_i\,\frac{1}{\theta(G,\mathcal{M}_i)},
$$
where \(\theta(G,\mathcal{M}_i)\) is the maximum concurrent-flow factor. Total completion time is
$$
T_{\rm coll}=s\,\alpha+\sum_{i=1}^s\delta\,\ell_i+\beta\sum_{i=1}^s m_i\,\frac{1}{\theta(G,\mathcal{M}_i)}.
$$
This places propagation delay, congestion, and reconfiguration overhead in one latency model rather than treating circuit switching as cost-free [2510.08072].

The same framework connects collective scheduling to Birkhoff–von Neumann decomposition. In pure form,
$$
\mathcal{M}=\sum_{k=1}^K \lambda_k\,P_k,
$$
while in collectives
$$
\mathcal{M}=\sum_{i=1}^s m_i\,\mathcal{M}_i
$$
is already a weighted decomposition into permutation matrices. The immediate systems interpretation is that naive reconfiguration before every step realizes one-hop, full-rate paths for each matching, but also incurs the full \(\alpha_r\) penalty at every step [2510.08072].

The optimization criterion is therefore conditional. The stated heuristic threshold is to switch when
$$
\Delta T_{\rm gain}=\beta\,m_i\Bigl(\tfrac{1}{\theta(G,\mathcal{M}_i)}-1\Bigr)
>\alpha_r+\delta(\ell_i-1).
$$
This formalizes a common misconception in discussions of photonic collectives: it is not generally optimal either to reconfigure before every matching or never to reconfigure. The simulation study reports a transitional diagonal regime in which an optimized schedule outperforms both extremes by up to \(2\text{–}5\times\) [2510.08072].

For all-to-all, the optimization problem is recast at a different abstraction level. Any candidate sequence of topologies and flow schedules can be written as
$$
A=\sum_{i=1}^d\sum_{j=1}^{s_i} M_{i,j}\odot(P_i)^{h_{i,j}},
$$
where \(A\) is the all-to-all traffic matrix, \(P_i\) are topology adjacency matrices, and \(h_{i,j}\) are hop counts. For \(k=1\), \(n\) nodes, and exactly \(d\) reconfigurations, the lower bound is
$$
TotalTime \ge d\cdot R + T\cdot\bigl[d\cdot(q(q+1)/2)+u\cdot(q+1)\bigr],
$$
with \(q=\lfloor(n-1)/d\rfloor\) and \(u=(n-1)\bmod d\). This work explicitly criticizes assumptions under which it is never or always worthwhile to reconfigure, and reports up to \(44\%\) reduction in all-to-all completion time on average across a wide range of network parameters, message sizes and workload types [2602.10468].

## 5. Demonstrated systems and representative metrics

The experimental literature spans nonvolatile photonic meshes, microring switch fabrics, MEMS Benes networks, and large-area glass interposers. The reported functions are not interchangeable: some platforms prioritize low-loss broadband switching, others self-configuration or coupled-cavity programmability, and others end-to-end panel reach or large-port-count spatial switching.

| Platform | Demonstrated function | Representative metrics |
|---|---|---|
| NEO-PGA | \(4\times4\) OCS, high-\(Q\) resonators, self-configurable beam sorting | \(16\) routings; crosstalk \(< -25\,\text{dB}\); \(Q_{\text{int}}\approx226{,}000\); beam-sorting crosstalk \(< -12\,\text{dB}\) |
| Microring \(8\times8\) fabric | Fully non-blocking silicon photonic switch | path IL \(\simeq13.5\text{–}14\,\text{dB}\); thermal tuning \(1\text{–}10\,\mu\text{s}\) |
| SWX MEMS \(64\times64\) Benes | High-port-count switch array | ON \(0.54\text{–}0.76\,\text{dB}\); OFF \(0.12\text{–}0.40\,\text{dB}\); ON \(3.5\,\mu\text{s}\), OFF \(1.2\,\mu\text{s}\) |
| Glass-panel WDM crossbar | Panel-edge-to-panel-edge interconnect | \(22.8\,\text{dB}(\pm0.2)\) measured IL; \(-26\,\text{dB}\) crosstalk; \(1.15\,\text{pJ/bit}\); \(0.79\,\text{Tb/s/mm}^2\) |

Within NEO-PGA, the circulating mesh is used as a broadband optical circuit switch over \(1335\text{–}1345\,\text{nm}\) with \(16\) routings and crosstalk \(< -25\,\text{dB}\). The same mesh realizes programmable ring resonators with \(Q_{\text{int}}\) up to \(226\,000\) and \(\text{FSR}\approx0.123\,\text{nm}\) for a \(2\,\text{mm}\) loop, plus dual rings with independent tuning and a coupled-cavity strong-to-weak coupling transition. The forward mesh sorts two orthogonal input vectors with crosstalk \(< -12\,\text{dB}\), and \(\le -14\,\text{dB}\) in best cases [2506.18592].

The \(8\times8\) microring switch demonstrates a path-independent loss rule in which every path traverses exactly \(N-1\) bar rings plus \(2\) cross rings, giving \(N+1=9\) rings for \(N=8\). The resulting end-to-end insertion loss is measured at \(\simeq13.5\text{–}14\,\text{dB}\) after polarization and resonance fine tuning, and the power penalty remains \(<0.5\,\text{dB}\) at \(\text{BER}=10^{-12}\) with six decorrelated crosstalk sources [1512.09323].

The MEMS split-waveguide-crossing switch reports OFF-state excess loss \(0.12\text{–}0.40\,\text{dB}\), ON-state excess loss \(0.54\text{–}0.76\,\text{dB}\), OFF-state crosstalk \(<-44\,\text{dB}\), ON-state crosstalk \(<-24.1\,\text{dB}\), threshold drive \(\simeq20\,\text{V}\), dynamic energy \(\simeq0.54\,\text{pJ}\), steady-state power \(<4\,\text{nW}\), and durability \(>10^9\) cycles. The associated \(64\times64\) Benes network is presented as a practical route to panel-scale interconnect and routing [2305.17366].

For the glass-panel interposer, the stated WDM parameter set uses \(N_w=32\) wavelengths, \(\Delta\lambda\simeq1\,\text{nm}\), and \(B_{ch}=32\,\text{Gb/s}\), giving \(B_{\text{total}}=1.024\,\text{Tb/s}\) per waveguide. The measured metrics listed for the \(500\,\text{mm}\) scale are \(22.8\,\text{dB}(\pm0.2)\) insertion loss, \(-26\,\text{dB}\) total crosstalk, \(1.15\,\text{pJ/bit}\), and \(0.79\,\text{Tb/s/mm}^2\), with a scaling estimate of \(+6\,\text{dB}\) insertion loss when moving from \(500\) to \(1000\,\text{mm}\) [2508.06079].

## 6. Scaling limits, packaging strategies, and unresolved issues

Scaling is constrained by gate density, loss accumulation, addressing granularity, and control latency. For the PCM-programmable MZI mesh, the gate footprint is \(\approx80\times50\,\mu\text{m}^2\), corresponding to \(\approx250\) gates/\(\text{mm}^2\) and \(\approx500\) nodes/\(\text{mm}^2\) when both arms are counted. The same estimate yields \(>10^6\) programmable gates on a \(300\,\text{mm}\) wafer and \(\approx25{,}000\) gates on a \(100\,\text{mm}\times100\,\text{mm}\) panel-scale patch. However, total on-board reconfiguration time is stated to be limited by serial pulse addressing, with \(1\,\text{ms}\times10^4\) gates \(=10\,\text{s}\) for full-panel reconfiguration unless parallel drivers or multiplexed addressing are introduced [2506.18592].

For resonant crossbars on glass, the principal limit is accumulated route loss rather than static-programming energy. The worst-case \(500\,\text{mm}\) path is modeled at \(23\,\text{dB}\), supported without active repeaters by injecting \(\approx0\,\text{dBm}\) per carrier, while doubling panel dimension to \(1000\,\text{mm}\) increases insertion loss by \(6\,\text{dB}\) and reduces bandwidth density by a factor of four. Thermal behavior is treated locally, with adjacent-node thermal crosstalk \(<0.1\,\text{K}\), panel-level fiducials and passive stops achieving \(\pm100\,\text{nm}\) lateral and \(\pm0.5\,\mu\text{m}\) vertical alignment, and edge couplers tolerating \(\pm200\,\text{nm}\) gap variation for \(>90\%\) efficiency [2508.06079].

For MEMS Benes networks, the panel-scale roadmap is explicitly modular. A \(64\times64\) die is \(\simeq10\times5.3\,\text{mm}^2\); a \(256\times256\) panel can be organized as a \(4\times4\) array of \(64\times64\) dies, or a \(2\times2\) array if each \(64\times64\) is folded. Proposed packaging elements include edge couplers plus low-loss polymer interposers across die boundaries, fiber-array interfaces or free-space microlens-array coupling, and hermetic metal packages with \(>40\) pins per die [2305.17366].

At the systems level, the unresolved issues are increasingly algorithmic. The adaptive-scale-up literature identifies the need for fast online heuristics approximating dynamic programming in \(O(s)\) or \(O(s\log s)\), lightweight proxies for \(\theta(G,\mathcal{M}_i)\), models with variable \(\alpha_r\), overlap between compute and reconfiguration, and multi-ported fabrics that support unions of multiple matchings per step. The all-to-all literature adds hierarchical local/global scheduling, staggered OSW pipelines to hide \(R\), fall-backs for latency-sensitive mice flows, and multi-tenant isolation through time slots or disjoint wavelength sets [2510.08072] [2602.10468].

A plausible implication is that “panel scale” is not a single hardware category but a co-design regime. The physical fabric, the programming mechanism, and the collective scheduler are coupled: low-static-power nonvolatile meshes reduce standby cost, MEMS and microrings offer different reconfiguration-delay regimes, and large-area WDM crossbars shift the bottleneck toward insertion loss and control orchestration rather than only switch count.

Source: https://www.emergentmind.com/topics/panel-scale-reconfigurable-photonic-interconnects