---
title: On-chip Reconfigurable Intelligent Surfaces (RIS)
url: https://www.emergentmind.com/topics/on-chip-reconfigurable-intelligent-surfaces-ris
type: topic
---

# On-chip Reconfigurable Intelligent Surfaces (RIS)

A CMOS-compatible on-chip reconfigurable intelligent surface (RIS) is a planar, electrically controlled metasurface device, fully compatible with CMOS fabrication flows, designed to impart programmable phase shifts to incident electromagnetic waves. Realized at 100 GHz, such RIS-on-chip systems exploit layered, lithographically defined structures incorporating switchable conductive oxides—here vanadium dioxide (VO₂)—to enable rapid, binary (1-bit) phase control with low loss and high system-level integration. These platforms are foundational for 6G sub-terahertz wireless communication, supporting monolithic beam steering within compact, CMOS-integrable form factors [2512.18854].

## 1. Unit-Cell Architecture and Electromagnetic Behavior

Each RIS unit cell consists of a hierarchical stack on high-resistivity silicon, enabling both CMOS compatibility and low-loss reconfigurability. The cross-sectional hierarchy is air → slot resonator → SiO₂ isolation layer → patterned Cu delay-line with integrated VO₂ patch → continuous Cu ground plane → Si substrate. Dimensional parameters are listed in Table 1.

| Parameter | Value      |
|-----------|------------|
| W_sub     | 1.125 mm   |
| h_si      | 300 µm     |
| h_sio₂    | 15 µm      |
| w_s       | 187.5 µm   |
| ℓ_s       | 562.5 µm   |
| w_d       | 30 µm      |
| ℓ_d       | 400 µm     |

The slot capacitively couples incident plane waves into the delay-line, with the VO₂ patch bridging a 30 µm gap. In the ON state (T > $T_c \approx 68 \,\mathrm{^\circ C}$), VO₂ exhibits $\sigma \approx 10^5$ S/m and shorts the meander, resulting in overall effective line length $\ell_{\text{eff}} = \ell_d$. In the OFF (insulating) state, $\sigma < 10^0$ S/m, and current detours an additional $\Delta \ell \approx 200\,µ$m, producing a differential electrical phase of approximately $\pi$ radians ($180^\circ$) at the design frequency $f_0 = 100.75$ GHz. The reflection coefficient at the slot port, deembedded to the reference plane, is given by
\[
\Gamma(f) = \frac{Z_{\text{unit}}(f) - Z_0}{Z_{\text{unit}}(f) + Z_0},
\]
with $Z_0 = 377\,\Omega$ and $Z_{\text{unit}}(f) \approx j Z_{\text{line}} \tan [\beta(f) \ell_{\text{eff}}]$ where $\ell_{\text{eff}}$ toggles between the two current paths. Full-wave HFSS simulations confirm a reflection magnitude $|\mathrm{S}_{11}| > -1.2$ dB in both states, with a simulated and measured phase difference of $180^\circ$ at $f_0$ over a bandwidth of $\approx2.5$ GHz [2512.18854].

## 2. Array-Level Synthesis and Beam Steering

The RIS comprises a $60 \times 60$ unit-cell array (3,600 cells), with planar cell pitch $p = 1.125$ mm ($\approx 0.375\,\lambda_0$ at 100.75 GHz), forming a $67.5\,\mathrm{mm} \times 67.5\,\mathrm{mm}$ aperture. VO₂ heating lines and control buses are confined within the SiO₂ interlayer to minimize parasitics and enable rapid addressability.

Beamforming is governed by the planar array factor:
\[
AF(\theta,\phi) = \sum_{m=1}^{M}\sum_{n=1}^{N} \exp\left\{ j \left[ k d (m \sin\theta \cos\phi + n \sin\theta \sin\phi ) + \phi_{mn} \right] \right\}
\]
where $\phi_{mn} \in \{0,\pi\}$ encodes the RIS cell binary phase state via VO₂ heating. Quantized phase patterns—implemented via programmable VO₂ states—steer the main lobe to arbitrary $(\theta_0,\phi_0)$ angles per reflectarray synthesis conventions. Simulated boresight directivity reaches $25.1$ dBi, with measured peak gain at $\theta_\text{scan}=0^\circ$ of $24.4$ dBi and half-power beamwidth of $1.8^\circ$. Sidelobe suppression approaches $-13$ dB, with scan-range peak gain variation within $\sim1.9$ dB up to $\theta_\text{scan}=30^\circ$ [2512.18854].

## 3. CMOS-Compatible Microfabrication

Fabrication adheres strictly to established CMOS and silicon micromachining protocols, ensuring full system-on-chip integration viability. The sequential process is as follows:

1. High-resistivity silicon wafer ($h_\mathrm{si}=300\,\mu$m) is coated with $200\,$nm sputtered Cu for the ground plane.
2. Photolithographic definition and lift-off patterning of the delay-line Cu.
3. $15\,\mu$m SiO₂ deposition via PECVD; lithographically patterned and selectively etched for via formation.
4. VO₂ is deposited (sputtering or ALD) exclusively within the delay-line gap, patterned by lift-off and annealed at ~350$^\circ$C to ensure stoichiometry.
5. Topside slot Cu deposition by lithography/sputtering/lift-off.
6. Optional encapsulation with thin SiO₂ or polymer for environmental passivation.

Optical micrographs confirm high yield and sub-micron overlay tolerances across both the $60 \times 60$ and reduced $5 \times 5$ test arrays [2512.18854].

## 4. Experimental Characterization and Performance Benchmarking

At normal incidence ($\theta=0^\circ$), ON/OFF reflection contrast exceeds $27.1$ dB at $f_0$, remaining above $20$ dB over an operational range of $98$–$103$ GHz. Single cell $|\mathrm{S}_{11}|$ is measured at about $-1.0$ dB, implying $\sim79\%$ reflection efficiency. Overall array aperture efficiency, accounting for edge taper and quantization loss, is $\sim65\%$.

VO₂ switching is thermally actuated with pulse energies $<50$ nJ per cell and switching times near $50$ ns; per-cell CW power handling is limited by VO₂ dissipation ($\sim100$ mW). Table 2 below summarizes comparative performance with recent RIS approaches.

| Reference               | $f_0$ (GHz) | Loss (dB) | Phase Resolution | CMOS Compat.    |
|-------------------------|-------------|-----------|------------------|-----------------|
| [2512.18854]            | 100.75      | 1.0       | 1-bit            | Yes             |
| Machado 2024            | 28          | 0.8       | 1-bit            | No (PCB)        |
| Gros 2021               | 28          | 2.5       | 1-bit            | No (MSS)        |
| Xu 2025 (liq. crystal)  | 300         | 3.2       | 1-bit            | No              |

The CMOS-compatible on-chip RIS achieves state-of-the-art loss and phase tunability at 100 GHz, with unique scalability benefits and integration capabilities [2512.18854].

## 5. Implications and Prospects for 6G Wireless Integration

Monolithic integration of the presented RIS with on-chip transceivers (e.g., VCOs, mixers) enables beam-steerable wireless links targeting 6G sub-terahertz networking. Control is managed by a CMOS decoder and SRAM architecture, reconfiguring all 3,600 cells in $<100$ μs aggregate time. The principal limitations are VO₂ array thermal management and the scale-dependent reduction of cell pitch and overlay accuracy at frequencies beyond 200 GHz.

Prominent future directions include:

- Multi-bit phase quantization via cascaded VO₂ or alternative materials, increasing angular steering resolution.
- Hybrid amplitude/phase control metasurfaces for improved sidelobe suppression and beam shaping.
- Adoption of sub-nanosecond switch technologies (fast-doped VO₂ or graphene-integrated switches).
- Optimization of thermal vias and micro-heater layouts to minimize switching latency and substrate heating under high duty-cycle operation.

A plausible implication is that such CMOS-compatible RIS devices, offering low loss, sub-wavelength pitch, and fully electronic addressability, will become foundational blocks in dense, high-frequency 6G chip-to-chip wireless interconnects and agile communication front-ends [2512.18854].

Source: https://www.emergentmind.com/topics/on-chip-reconfigurable-intelligent-surfaces-ris