---
title: Neuromorphic Intermediate Representation (NIR)
url: https://www.emergentmind.com/topics/neuromorphic-intermediate-representation-nir
type: topic
---

# Neuromorphic Intermediate Representation (NIR)

Neuromorphic Intermediate Representation (NIR) is a standardized, hardware-agnostic model description formalism for specifying, manipulating, and deploying neuromorphic algorithms—particularly Spiking Neural Networks (SNNs)—across heterogeneous simulation environments and digital neuromorphic hardware platforms. NIR enables reproducible, cross-platform research by providing a unifying, mathematically rigorous abstraction that captures both the continuous-time dynamics and discrete event-driven behaviors characteristic of neuronal systems, while systematically decoupling algorithmic specifications from backend discretization, precision, and architectural idiosyncrasies [2311.14641][2504.06748][2604.03432].

## 1. Mathematical Foundations and Formalism

NIR models every component of a neuromorphic system as a *hybrid* dynamical system, combining ordinary differential equations (ODEs) for continuous-time state evolution and instantaneous, event-triggered state transitions such as spike-induced resets. Specifically, each NIR computational primitive $c \in \mathcal{C}$ is defined by:

- A set of continuous state variables $x(t) \in \mathbb{R}^{N_x}$, evolving according to
  $$
  \dot x = f_\theta(x, u(t))
  $$
  where $u(t)$ is a continuous input and $\theta$ encodes model parameters
- Event-trigger conditions:
  $$
  g_\theta(x, u(t)) = 0 \implies x \mapsto h_\theta(x, u(t))
  $$
  describing jumps or resets.

For instance, a Leaky Integrate-and-Fire (LIF) neuron primitive is defined as:
- Continuous dynamics:
  $$
  \tau \frac{dv}{dt} = (v_{\rm leak} - v) + R i(t)
  $$
- Discrete thresholding and reset rules:
  $$
  s(t) = \delta(v(t) - \theta_{\rm thr})
  $$
  with either hard reset $v(t^+) = 0$ or subtractive reset $v(t^+) = v(t) - \theta_{\rm reset}$ when threshold is crossed.

NIR provides both ideal continuous-time descriptions and canonical discrete approximations (e.g., Euler, exponential Euler), with explicit formulas mapping abstract parameters to backend-specific representations (e.g., fixed-point weights, surrogate gradients, discretized time constants) [2311.14641][2504.06748].

## 2. Instruction Set and Core Primitives

NIR defines a composable palette of parametric primitives, which serve as the "instruction set" for neuromorphic computation. These primitives fall into three broad categories:

- **Stateless linear and spatial operators**: Input, Output, Affine, Linear, Convolution, Scale, Flatten, Delay. Each exposes a shape-annotated port-based interface and operates arithmetically on its input (e.g., $y = W u + b$ for affine).
- **Stateful continuous-time primitives**: Integrator, Leaky Integrator (LI), and Spike/Threshold. Defined by (potentially stiff) ODEs together with event-driven ports.
- **Composite neuron models**: IF (Integrate-and-Fire), LIF, CuBa-LIF, typically defined as compositions (e.g., LIF = Reset ∘ Threshold ∘ Leaky Integrator).

Table: Representative NIR Primitives and Their Key Parameters

| Primitive      | Parameters                              | Ports (I/O)                 |
|----------------|-----------------------------------------|-----------------------------|
| Input          | shape                                   | out                         |
| Affine         | $W$, $b$                                | in → out                    |
| Convolution    | kernel, stride, padding, dilation, bias | in → out                    |
| LIF            | $\tau$, $R$, $v_{\rm leak}$, $\theta_{\rm thr}$, reset | I (current), S_out (spike)  |
| Synapse        | $W$, delay                              | S_in (spike), I_out (curr)  |
| Delay          | d (delay steps)                         | S_in → S_out                |

The explicit, port-based design and direct mapping of neuron and synapse attributes enable unambiguous serialization and code generation for a wide portfolio of simulators and hardware targets [2311.14641][2604.03432].

## 3. Dataflow Graph Model and Serialization

NIR expresses an SNN or general neuromorphic system as a directed graph $\mathcal{G} = (\mathcal{V}, \mathcal{E})$:
- $\mathcal{V}$: Nodes, each associated to a primitive and a set of concrete parameter values.
- $\mathcal{E}$: Edges, each connecting output ports to input ports, and carrying type- and shape-annotated signals (tensors, events, or states).

A typical NIR model serialization (usually in JSON or equivalent) includes:
- Node definitions with IDs, primitive types, parameter dictionaries, named in/out ports
- Edge list specifying (source_node, src_port) → (destination_node, dst_port)
- Input node and output node specification
- Optional metadata: quantization scales, delays, reset mechanisms, event routing information

This organization supports direct code generation and transformation passes (quantization, hardware lowering, parameter rescaling) [2311.14641][2504.06748][2604.03432].

## 4. Quantization, Metadata, and Transformation Passes

NIR maintains all parameter values in either full-precision or quantized forms, tracked as node metadata. The standardized representation is essential for efficient deployment on constrained digital neuromorphic platforms.

- **Quantization formats**: Node attributes may carry full-precision weights $w_{NIR}$, quantized values $w_{q}$, and associated scaling factors $\lambda_s$ or $S_i$ (percentile- or learned-scaling) [2504.06748].
- **Post-Training Quantization (PTQ)**: Weights rescaled by
  $$
  w_{S2} = \lambda_s \cdot w_{NIR}, \quad \lambda_s = 127 / P_w(p)
  $$
  (where $P_w(p)$ is the $p$th percentile), with LIF thresholds $\Gamma$ also scaled by $\lambda_s$. Quantization metadata is stored in the NIR graph for precise code emission.
- **Quantization-Aware Training (QAT)**: Linked full-precision/quantized weight pairs, straight-through estimator for gradients, per-layer scaling $S_i$, layerwise LIF threshold adaptation
  $$
  \Gamma_i \leftarrow \Gamma_i / S_i
  $$
  (see Algorithm 1 in [2504.06748]). All relevant quantities are tracked within NIR nodes.

These passes are automated at the NIR level and facilitate backend targeting without loss of algorithmic fidelity.

## 5. Cross-Platform Interoperability and Deployment

A core property of NIR is backend-agnosticism: the same NIR model can be compiled, unchanged, for a wide spectrum of software simulators (e.g., Lava, Nengo, Norse, snnTorch, Rockpool) and digital neuromorphic hardware (SpiNNaker2, AMD Kria via YANA, Loihi, Xylo) [2311.14641][2604.03432].

Notable outcomes:
- Empirical equivalence in spike times, membrane voltage traces, and test accuracy across platforms for standard benchmarks (e.g., ≥98% accuracy on N-MNIST SCNN, near-identical firing patterns for LIF single neuron) [2311.14641].
- Rapid translation from high-level frameworks (PyTorch, Brevitas, Norse) into NIR—then into hardware via per-backend 'emitters', obviating $O(M \times N)$ bespoke translators.
- Hardware resources and schedules (e.g., SRNN mapping, pipeline timing, sparse event routing) are generated by traversing the NIR graph, with performance optimizations such as blockwise buffer allocation, fused LUT-based leak, and pruning/weight sharing recognized at deploy time [2604.03432].

## 6. Exemplars: SpiNNaker2 and FPGA Pipelines

Deployment pipelines utilizing NIR illustrate its end-to-end expressivity:
- **SpiNNaker2**: NIR graphs are quantized with PTQ or QAT, mapping LIF nodes to M4F core populations and convolution/linear projections. All quantization metadata, delays, and thresholds are directly processed from NIR, achieving 4× model size reduction with ≤1% accuracy drop and sub-joule inference energy per gesture (DVS-Gesture, 94% on-chip accuracy) [2504.06748].
- **YANA (FPGA on AMD Kria)**: NIR is parsed, nodes partitioned and memory-mapped (URAM for weights, BRAM for neuron states), and event-driven stages (RX, Synapse, Neuron, Axon, TX) synthesized. LUT-based leak computation, native weight sharing, and pruning directives are handled at the NIR level. Sustained throughput is one event per cycle, with resource-efficient mapping for up to $2^{17}$ synapses and $2^{10}$ neurons per core [2604.03432].

## 7. Benefits, Current Limitations, and Extension Trajectories

NIR provides:
- Clear separation between algorithmic model and implementation, enabling portable, comparable, and verifiable research and deployment [2311.14641][2504.06748][2604.03432].
- Unified reference semantics for continuous-time, event-driven neuromorphic systems.
- Precise, typed, and extensible representations suited to compiler-based toolchains.

However:
- NIR does not enforce strict bitwise-equivalence across platforms: discretization/integration and numeric precision may still yield subtle behavioral divergence [2311.14641].
- Restricted to a fixed primitive palette (LIF, CuBa-LIF, etc.); explicit representation of advanced plasticity, learning rules, or conductance synapses requires further compositional constructs.
- No built-in support for analog or hybrid (mixed-signal) backends.

Proposed extensions include broadening primitive sets (adaptation/plasticity), introducing formal mismatch specifications for backend drift, tighter integration of quantization and calibration tooling, and evolution into a compiler intermediate representation with support for algebraic graph optimizations and deployment scheduling [2311.14641].

---

**Key References:**  
- “Neuromorphic Intermediate Representation: A Unified Instruction Set for Interoperable Brain-Inspired Computing” [2311.14641]  
- “Efficient Deployment of Spiking Neural Networks on SpiNNaker2 for DVS Gesture Recognition Using Neuromorphic Intermediate Representation” [2504.06748]  
- “YANA: Bridging the Neuromorphic Simulation-to-Hardware Gap” [2604.03432]

Source: https://www.emergentmind.com/topics/neuromorphic-intermediate-representation-nir