---
title: Multi-Channel Readout Chip (MCRC) Overview
url: https://www.emergentmind.com/topics/multi-channel-readout-chip-mcrc
type: topic
---

# Multi-Channel Readout Chip (MCRC) Overview

Searching arXiv for recent and foundational papers on multi-channel readout chips across detector domains.
A Multi-Channel Readout Chip (MCRC) is an integrated readout device that services multiple detector channels in parallel and, depending on the application, can combine front-end amplification, shaping, discrimination, digitization, buffering, trigger logic, multiplexing, and data-reduction functions on the same chip or in a tightly coupled readout module. In the literature, the term spans semi-digital ASICs for resistive-plate chambers, waveform-sampling chips for Cherenkov cameras and MCP detectors, low-noise analog front ends for X-ray CCD-like sensors, cryogenic skipper-CCD readout ASICs, and high-density SoC digitizers for picosecond photodetectors [1605.06235] [1105.1832] [2407.16759] [2304.13088] [2406.11067] [2511.22765]. The unifying idea is architectural consolidation: many detector channels are handled locally, with reduced external cabling, controlled noise, and a readout format matched to detector occupancy and timing.

## 1. Detector-driven meaning and scope

The meaning of an MCRC is determined primarily by detector topology and system scale. In the INO-ICAL case, the requirement arises from about 29,000 glass RPC detectors of \(2\,\mathrm{m} \times 2\,\mathrm{m}\), each with 64 readout channels in \(X\) and 64 in \(Y\), making detector-embedded, low-line-count readout mandatory; HARDROC was evaluated there as a 64-channel semi-digital ASIC with on-chip zero suppression and daisy-chain communication [1605.06235]. In MPGD tracking, SALSA was defined as a 64-channel chip for the EPIC experiment at the EIC, with continuous-streaming compatibility, per-channel ADCs, and a configurable DSP to manage output bandwidth under signal rates of order \(10\,\mathrm{kHz}\) and time resolution of order \(10\,\mathrm{ns}\) [2501.10237].

In X-ray instrumentation, the same term denotes a compact analog front end integrated close to CCD outputs. The Stanford MCRC for MIT Lincoln Laboratory detectors was developed as an 8-channel ASIC that biases the detector output stage, amplifies the signal, and drives an external ADC, with selectable source-follower and drain-current input modes for conventional CCDs and SiSeRO devices [2407.16759] [2508.14173]. In skipper-CCD work, MIDNA is explicitly framed as a multi-channel readout chip specialized for repeated non-destructive sampling, cryogenic operation, and sub-electron noise [2304.13088].

Other instances broaden the concept rather than contradict it. GRAPH is a 16-channel mixed-signal readout ASIC for crossed-strip MCP detectors, where the essential requirement is waveform capture with local buffering and region-of-interest extraction [2406.11067]. TARGET is a 16-channel, GSa/s switched-capacitor-array digitizer for Cherenkov telescope cameras, where the MCRC is defined by deep analog storage, self-triggering, and tight windowed readout [1105.1832]. Commercial parts can also occupy the same functional niche: ADAS1128 was used as a 128-channel current-integrating front end for Micromegas muon imaging, and Nalu’s HDSoC and AARDVARC were used as multi-channel waveform digitizers for second-generation LAPPDs [2405.12454] [2511.22765].

## 2. Common circuit architecture

Despite the diversity of detector modalities, MCRCs repeatedly instantiate a per-channel analog chain that conditions a small detector signal before thresholding or digitization. HARDROC provides a variable-gain preamplifier per channel with gain up to \(\times 2\), 8-bit per-channel tuning, three fast CR-RC shapers with peaking time \(\approx 20\)–\(25\,\mathrm{ns}\), three low-offset discriminators, and one slow shaper with \(50\)–\(150\,\mathrm{ns}\) shaping and track-and-hold for analog diagnostic output up to \(10\,\mathrm{pC}\) [1605.06235]. SALSA uses a charge-sensitive amplifier, pole-zero cancellation stage, and shaper, offers four gain ranges from \(0\)–\(50\,\mathrm{fC}\) to \(0\)–\(5\,\mathrm{pC}\), and eight selectable peaking times between \(50\,\mathrm{ns}\) and \(500\,\mathrm{ns}\) [2501.10237].

For X-ray CCD-like sensors, the front end is usually analog and differential rather than threshold-centric. MCRC-V1 implements selectable voltage-input and current-input stages, on-chip bias generation for the detector output transistor, a fully differential preamplifier with two gain settings, and a unity-gain differential output buffer able to drive a \(100\,\Omega\) line directly into an external ADC [2407.16759]. In the SiSeRO drain-current mode, the chain is further specialized into an active cascode, programmable current source, \(100\,\mathrm{k}\Omega\) current-to-voltage amplifier, AC coupling, differential preamplifier, and output buffer [2508.14173].

Cryogenic skipper-CCD readout pushes the architecture in a different direction. MIDNA integrates four channels, each containing a folded-cascode preamplifier, a DC restorer, and a dual-slope integrator with chopping to suppress low-frequency noise generated inside the integrator itself [2304.13088]. GRAPH, by contrast, combines a programmable fast charge-sensitive front end with the Hybrid Universal sampLing Architecture, where each sample cell incorporates a sampling capacitor, local comparator, overwrite-protection logic, and a 12-bit digital register [2406.11067]. TARGET uses per-channel switched-capacitor-array storage and Wilkinson conversion; here the buffer architecture rather than the preamplifier topology defines the chip [1105.1832].

This diversity indicates that “multi-channel” is not a single circuit template. It is a systems category in which the analog chain, memory organization, and trigger path are specialized to the detector’s signal duration, expected occupancy, and downstream bandwidth.

## 3. Readout modes, triggering, and data reduction

A central distinction among MCRCs is whether they perform thresholded, integrated, or waveform-based readout. HARDROC is a semi-digital design. Each channel has three thresholds set by internal 10-bit DACs, and discriminator outputs are fed to a 3-inputs-to-2-outputs encoder that generates 2-bit semi-digital coding. The chip evaluates the status of the 64 lowest-threshold comparators every \(200\,\mathrm{ns}\); if any fires, the 64-channel data are captured, stored in a 128-deep digital memory, and frames with no fired channels are not stored, thereby implementing zero suppression [1605.06235].

SALSA represents the opposite pole: per-channel waveform digitization followed by on-chip digital processing. Each of its 64 channels includes a 12-bit SAR ADC operating from \(5\,\mathrm{MS/s}\) to \(50\,\mathrm{MS/s}\), and the chip-level DSP performs pedestal equalization, common-mode noise subtraction, baseline following, IIR filtering, low-amplitude sample suppression, and feature extraction of amplitude, time of arrival, and signal width [2501.10237]. GRAPH likewise stores sampled waveforms locally, with 2048 samples per channel, a sampling frequency adjustable from a few kHz up to \(125\,\mathrm{MHz}\), and a region-of-interest sample-read algorithm that extracts only the samples around the pulse peak while the next event is being selected [2406.11067]. TARGET extends waveform-centric readout to the GSa/s regime, with 4096 samples per channel in TARGET~1 and 16384 samples per channel in TARGET~2, plus self-trigger functionality and tight window-selected digitization [1105.1832].

Other MCRCs use digitization outside the chip, or integrate over a fixed window instead of sampling a waveform. The Stanford X-ray MCRC explicitly omits analog CDS/DSI on the ASIC; the analog differential output is digitized externally, and CDS or optimal filtering is applied in the controller or off-line [2407.16761]. ADAS1128 integrates 128 current amplifiers, sample/hold stages, and two 24-bit ADCs, but its operating principle is current integration over a programmable window from \(50.7\,\mu\mathrm{s}\) to \(900\,\mu\mathrm{s}\), with the results from cycle \(N\) output during cycle \(N+2\), ensuring no dead time or charge loss [2405.12454].

A recurring implication is that on-chip ADCs are not a defining requirement. Some MCRCs are front-end-plus-buffer devices, some are front-end-plus-ADC-plus-DSP devices, and some are mixed-signal samplers whose digitization is tightly coupled to storage and trigger control.

## 4. Integration, bandwidth, and scaling

MCRCs are often justified less by single-channel performance than by the way they collapse a large detector system into manageable modules. HARDROC was evaluated precisely because detector-embedded electronics and daisy-chain interconnection reduce external I/O lines for a detector system approaching \(29{,}000\) RPCs; the chip was implemented as a COB on a 6-layer PCB with FPGA-based readout and control [1605.06235]. The same integration logic appears in SALSA, where local DSP is required because the raw data flux at \(64 \times 50\,\mathrm{MS/s} \times 12\) bits is \(\approx 38.4\,\mathrm{Gb/s}\), far above the chip’s maximum \(4\,\mathrm{Gb/s}\) aggregate output provided by up to four \(1\,\mathrm{Gb/s}\) serial links [2501.10237].

High-energy-physics pixel systems show the same pattern at much higher link speed. The CMS Phase-2 pixel readout chip is controlled through a single \(160\,\mathrm{Mb/s}\) electrical downlink and transmits through four \(1.28\,\mathrm{Gb/s}\) CML uplinks, for \(5.12\,\mathrm{Gb/s}\) aggregate outbound bandwidth per chip, over low-mass twisted-pair links up to \(1.6\,\mathrm{m}\) long and tested to \(2.0\,\mathrm{m}\) [2110.14021]. In scalable MPGD systems, the ASIC is only one tier in a hierarchy: the SRS architecture uses ASIC cards, Adapter cards, and FPGA-based Front-End Cards, with one FEC covering 512 channels in the VA140 prototype or 256 channels with AGET, and 17 FECs in a chassis yielding 8704 prototype VA140 channels or 17408 channels if all 64 channels per chip are bonded out [1602.01437].

Large skipper-CCD systems demonstrate the scaling pressure from another angle. The OSCURA packaging study does not present a dedicated MCRC, but it defines the environment a future MCRC would have to inhabit: 1500 multi-chip modules, 16 skipper-CCDs per module, and 24000 readout channels in total, with a total readout time of \(\approx 2\) hours and a target noise of \(\approx 0.15\,e^{-}\,\mathrm{RMS}\) per pixel [2410.06417]. For Gen-II LAPPDs, commercial SoC readouts show a different scaling trade-off: HDSoC offers 32 channels in the board used, with a 64-channel second revision existing, while AARDVARC offers 4 channels in the evaluation board and 8-channel variants, reflecting the usual channel-density versus timing-performance compromise [2511.22765].

## 5. Performance regimes and design trade-offs

The most persistent MCRC design trade-off is among noise, bandwidth, dynamic range, and power. HARDROC reached practical threshold settings down to \(\approx 5\,\mathrm{fC}\), corresponding to \(\approx 5\sigma\) noise, with auto-trigger capability down to \(\approx 4\,\mathrm{fC}\); gain equalization reduced channel-to-channel dispersion of the threshold inflection point from \(11.4\) to \(8.8\) for \(100\,\mathrm{fC}\) injection, and calibration gave \(1\,\mathrm{fC} \approx 1.22\) DAC units at gain \(=1\) [1605.06235]. Yet the same work explicitly does not report cosmic-muon efficiency, timing resolution with real RPC signals, quantitative crosstalk, or per-chip power consumption, illustrating that MCRC validation is often staged rather than final.

SALSA exposes a more explicit bandwidth budget. The front-end prototype measured an ENC of \(\sim 1200\,e^{-}\) under typical MPGD conditions, while the full chip targets \(5\)–\(50\,\mathrm{MS/s}\) sampling, \(>10\) effective bits in the operating range, and \(\sim 15\,\mathrm{mW/channel}\) at \(1.2\,\mathrm{V}\). Because the output bandwidth is capped at \(4\,\mathrm{Gb/s}\), practical operation depends on the occupancy factor and DSP compression factor, not only on analog noise [2501.10237]. GRAPH illustrates a related compromise: it achieves \(\sim 47\,\mathrm{mW/channel}\), a nominal \(0\)–\(50\,\mathrm{fC}\) input range, 2048 samples per channel, and \(125\,\mathrm{MHz}\) sampling, but the measured usable analog headroom is \(\approx 800\,\mathrm{mV}\), the ADC noise after pedestal calibration is \(\approx 6\,\mathrm{mV}\), and the effective ENOB is \(\sim 7\) bits due to comparator offsets, ramp distribution, and occasional conversion outliers [2406.11067].

In X-ray CCD work, the trade-off is commonly expressed as speed versus read noise at fixed spectroscopic performance. MCRC V1 coupled to CCID-93 achieved \(2.6\,e^{-}\,\mathrm{rms}\) read noise at \(2\,\mathrm{Mpixel/s}\) per output and Fe-55 FWHM of \(124.9\)–\(125\,\mathrm{eV}\), with performance virtually identical to the group’s best discrete amplifier implementation [2407.16761]. The later MCRC-V1 study reports total ASIC power of \(\approx 0.35\,\mathrm{W}\) at optimal bias for eight channels, compared with \(\approx 4\,\mathrm{W}\) for the discrete eight-channel solution, and demonstrated radiation tolerance at least up to \(\approx 50\,\mathrm{krad}\) TID with no digital bit errors and minimal analog drift up to \(\approx 25\,\mathrm{krad}\) [2407.16759]. The SiSeRO extension preserved comparable performance at \(625\,\mathrm{kpixel/s}\), with ENC \(\approx 3.5\,e^{-}\,\mathrm{RMS}\) and FWHM \(\approx 134\,\mathrm{eV}\) at \(5.9\,\mathrm{keV}\), and pushed the drain-current mode to \(1\,\mathrm{Mpixel/s}\) with ENC \(\approx 4.9\,e^{-}\,\mathrm{RMS}\) and FWHM \(\approx 149\,\mathrm{eV}\) [2508.14173].

At the extreme low-noise end, MIDNA showed \(\sigma \approx 0.20\,e^{-}\,\mathrm{RMS}\) with \(N=1000\) skipper samples at room temperature, \(\sigma \approx 0.206\,e^{-}\,\mathrm{RMS}\) at \(\approx 183\,\mathrm{K}\) using residual cancellation, and \(\sigma \approx 0.196\,e^{-}\,\mathrm{RMS}\) using analog pile-up, while consuming \(\approx 4.2\)–\(4.5\,\mathrm{mW}\) per channel [2304.13088]. For picosecond photodetection, the limiting metric becomes timing rather than ENC: AARDVARC achieved electronics-only pair jitter of \(\sigma = 79\,\mathrm{ps}\) in internal-trigger mode and \(\sigma = 51\,\mathrm{ps}\) in external-trigger mode, whereas LAPPD pair jitter at SPE-level coincidence was typically \(\ge 100\,\mathrm{ps}\) and often several hundred picoseconds, showing that detector statistics and trigger logic can dominate even when the MCRC-class digitizer itself is fast [2511.22765].

A plausible implication is that MCRC design is usually constrained less by any single figure of merit than by the shape of the full operating envelope: occupancy, trigger strategy, calibration method, external interconnect, and acceptable dead time are often as decisive as nominal front-end noise.

## 6. Variants, boundary cases, and development directions

The term “MCRC” is broad enough that boundary cases matter. Not every multi-channel readout solution is a monolithic ASIC with one ADC per channel, and not every such chip is optimized for the same abstraction of a “channel.” In spin-qubit readout, for example, channelization can be frequency-domain rather than time-domain: an on-chip multiplexing network integrates a bias tee and LC resonator per channel so that multiple rf-QPC and dispersive gate sensors share a single \(50\,\Omega\) line, with channel identity defined by resonance frequency rather than replicated baseband front ends [1312.5064]. Conversely, a system such as the 20:1 LMH6574 multiplexer for directional dark-matter TPCs is not a detector-specific ASIC at all, but it still demonstrates MCRC-like design constraints such as switch dead time, grounding, and preservation of charge-distribution asymmetry after de-multiplexing [1711.00943].

A concise cross-section of representative implementations is given below.

| Implementation | Detector context | Characteristic features |
|---|---|---|
| HARDROC | RPCs for INO-ICAL | 64 channels, three thresholds, zero suppression, 128-deep memory |
| SALSA | MPGD for EPIC/EIC | 64 channels, 12-bit ADC per channel, DSP, up to \(4\,\mathrm{Gb/s}\) output |
| MCRC-V1 | MIT-LL CCDs and SiSeRO | 8 channels, selectable SF/DR input, external ADC |
| MIDNA | Skipper-CCD | 4 channels, DSI, chopping, cryogenic sub-electron readout |
| GRAPH | Crossed-strip MCP | 16 channels, HULA memory, ROI extraction |
| TARGET / TARGET~2 | IACT cameras | 16 channels, GSa/s SCA, self-trigger, windowed readout |

Current development directions preserve the same detector-driven specialization. SALSA’s roadmap proceeds through a 32-channel prototype in 2025, a full-channel pre-series in 2026, and production at the horizon of 2027 [2501.10237]. The next X-ray MCRC iteration expands the channel count from 8 to 16, adds per-output enable/disable control, an internal temperature sensor, and on-chip reset-gate clock drivers [2407.16759]. In SiSeRO work, the next revision is expected to address the I2V resonance seen in the first drain-current tests and to support integrated, parallel RNDR for multi-output CCD and APS variants [2508.14173]. In large skipper-CCD experiments, the silicon package work implies that any future MCRC must tolerate video-line capacitances of \(111\)–\(276\,\mathrm{pF}\), operate within a 24000-channel architecture, and preserve \(\sigma_N = \sigma_{N=1}/\sqrt{N}\) behavior over large skipper-sample counts while remaining compatible with low-background packaging constraints [2410.06417].

Taken together, these developments show that an MCRC is best understood not as a single chip family, but as a design class: a detector-proximate, many-channel readout engine whose analog front end, local memory, trigger logic, and data path are co-optimized for a specific measurement regime.

Source: https://www.emergentmind.com/topics/multi-channel-readout-chip-mcrc