---
title: MoS₂ Charge-Trap Memory Fundamentals
url: https://www.emergentmind.com/topics/mos-charge-trap-memory
type: topic
---

# MoS₂ Charge-Trap Memory Fundamentals

Searching arXiv for recent and foundational papers on MoS$_2$ charge-trap memory and adjacent mechanisms.
arXiv search: "MoS2 charge trap memory HfO2 Al2O3"
MoS\(_2\) charge-trap memory is a class of nonvolatile memory in which a MoS\(_2\) field-effect transistor functions as the readout element while information is stored as charge in a nearby storage medium that electrostatically shifts the threshold voltage or channel conductance. In the arXiv literature, the most direct embodiments are a few-layer dual-gate MoS\(_2\) memory using an Al\(_2\)O\(_3\)/HfO\(_2\)/Al\(_2\)O\(_3\) charge-trap stack and an all-2D monolayer MoS\(_2\)/graphene floating-gate memory, while a broader surrounding literature examines interface traps, oxide traps, photodoping, ionic motion, and memristive defect dynamics that can produce memory-like states in MoS\(_2\) devices [1407.7432, 1303.4799].

## 1. Canonical forms and scope

Within the strictest usage, MoS\(_2\) charge-trap memory refers to transistor memories in which stored charge is written electrically and read through a persistent threshold-voltage or current shift of a MoS\(_2\) channel. Two device lineages dominate the early arXiv record. One is a few-layer MoS\(_2\) top-gated memory transistor with a conventional high-\(k\) Al\(_2\)O\(_3\)/HfO\(_2\)/Al\(_2\)O\(_3\) stack, where HfO\(_2\) is the trap medium and the back gate tunes the apparent memory response [1407.7432]. The other is a fully 2D nonvolatile cell in which monolayer MoS\(_2\) is the semiconducting channel, graphene forms the source and drain contacts, and multilayer graphene serves as the floating charge-storage layer above a HfO\(_2\) tunnel dielectric [1303.4799].

The first architecture is a conventional charge-trap memory in the SONOS-like sense: the storage function resides in a trap-rich dielectric, the program and erase operations are field-driven, and the memory window is a threshold shift in a MoS\(_2\) FET. The second is a floating-gate memory rather than a distributed trap-layer memory, but it belongs to the same broader charge-storage family because information is stored as isolated charge and read electrostatically through the MoS\(_2\) transistor [1303.4799].

A larger body of MoS\(_2\) memory literature falls outside this narrow definition. Persistent photoconductivity devices, photodoping memories, irradiation-induced oxide-trap memories, thermally activated ion-modulated memtransistors, and grain-boundary memristors all generate nonvolatile or long-lived states in MoS\(_2\), but they do not all use a dedicated tunnel-dielectric/trap-layer/blocking-dielectric stack. That distinction is essential because identical observables—hysteresis, threshold shift, or multilevel conductance states—can arise from different physical reservoirs of stored state.

## 2. Device architectures and materials stacks

The dual-gate few-layer MoS\(_2\) charge-trap memory uses a degenerately doped Si substrate as the back gate, \(270\) nm SiO\(_2\) as the back-gate dielectric, a few-layer MoS\(_2\) flake identified as approximately \(3\)–\(4\) layers, Cr/Au source and drain contacts of \(12/100\) nm, and a local top-gate stack of \(7/8/30\) nm Al\(_2\)O\(_3\)/HfO\(_2\)/Al\(_2\)O\(_3\), followed by a Cr/Au top-gate electrode of \(12/100\) nm [1407.7432]. In this stack, the \(7\) nm Al\(_2\)O\(_3\) is the tunneling layer, the \(8\) nm HfO\(_2\) is the charge-trap layer, and the \(30\) nm Al\(_2\)O\(_3\) is the blocking layer. The device is explicitly dual-gated: the top gate programs and erases the HfO\(_2\) storage medium, while the Si back gate tunes channel electrostatics and therefore the measured memory window and current ratio [1407.7432].

The all-2D floating-gate memory is built on heavily doped \(p^{++}\)-Si with \(270\) nm thermal SiO\(_2\). Patterned CVD graphene stripes about \(3~\mu\)m wide and spaced by \(2~\mu\)m act as source and drain electrodes. A monolayer MoS\(_2\) flake bridges adjacent graphene stripes and forms the transistor channel. Above the channel lies a tunnel stack described as approximately \(1\) nm Al\(_2\)O\(_3\) plus \(6\) nm HfO\(_2\), then a multilayer graphene floating gate about \(1.5\) nm thick, corresponding to roughly \(4\)–\(5\) graphene layers, then a blocking stack of about \(1\) nm Al\(_2\)O\(_3\) plus \(30\) nm HfO\(_2\), and finally a Cr/Au top control gate [1303.4799]. This architecture is “fully 2D” in the sense that the active semiconductor channel, the lateral contacts, and the floating gate are all graphitic or layered van der Waals materials.

A later comparative study on few-layer black phosphorus is frequently relevant to MoS\(_2\) because it isolates the transferable value of the Al\(_2\)O\(_3\)/HfO\(_2\)/Al\(_2\)O\(_3\) concept. That device used a \(5/8/35\) nm Al\(_2\)O\(_3\)/HfO\(_2\)/Al\(_2\)O\(_3\) stack deposited by ALD at \(120^\circ\)C, with the \(5\) nm Al\(_2\)O\(_3\) as tunnel oxide, \(8\) nm HfO\(_2\) as trap layer, and \(35\) nm Al\(_2\)O\(_3\) as blocking oxide; the study explicitly argued that the stack design, tunneling mechanism, retention methodology, and trapped-charge estimation were directly transferable to MoS\(_2\) memory design [1511.07619].

## 3. Storage physics and program/erase mechanisms

In the few-layer MoS\(_2\) Al\(_2\)O\(_3\)/HfO\(_2\)/Al\(_2\)O\(_3\) memory, the dominant mechanism is field-driven tunneling between the MoS\(_2\) channel and the HfO\(_2\) storage layer through the \(7\) nm Al\(_2\)O\(_3\) tunnel oxide. Positive top-gate bias causes electrons in the MoS\(_2\) channel to tunnel through the tunnel oxide into HfO\(_2\) via Fowler–Nordheim tunneling, producing a positive threshold shift and the programmed state. Negative top-gate bias drives previously trapped electrons back and also enables holes to tunnel into HfO\(_2\), producing a negative threshold shift. The large memory window therefore reflects bidirectional storage: electron trapping on one side of the hysteresis and hole trapping on the other [1407.7432].

That work estimates stored charge density from threshold shift using
\[
n = \frac{\Delta V \times C_{HF-AL}}{e},
\qquad
C_{HF-AL} = \frac{\varepsilon_0 \varepsilon_{AL}}{d_{AL}},
\]
where \(C_{HF-AL}\) is the capacitance between the HfO\(_2\) trap layer and the top gate through the blocking Al\(_2\)O\(_3\), \(\varepsilon_{AL}\sim 8\), and \(d_{AL}\sim 30\) nm [1407.7432]. The dynamic trapping rate is extracted from
\[
\frac{dN_{\text{trap}}}{dt}
=
\frac{C_{HF-AL}}{e}
\left(
\frac{\Delta V_{TH}}{\Delta t}
\right).
\]
This methodology became a template for subsequent MoS\(_2\) charge-storage analysis because it links a directly measured transfer-curve shift to an areal charge density and to pulse-width-dependent injection kinetics [1407.7432].

In the all-2D floating-gate device, positive control-gate bias accumulates electrons in the \(n\)-type monolayer MoS\(_2\) channel and lowers the tunnel barrier sufficiently for electrons to tunnel through HfO\(_2\) into the multilayer graphene floating gate. Negative control-gate bias discharges the floating gate by driving electrons back to the MoS\(_2\) channel. The state is read as a threshold shift in \(I_{ds}(V_{cg})\), and the stored electron density is estimated by
\[
n = \frac{\Delta V \, C_{FG-CG}}{q},
\qquad
C_{FG-CG} = \frac{\varepsilon_0 \varepsilon_{bl}}{d_{bl}}.
\]
Using this framework, the work interpreted the storage node as a deep graphene-related potential well, with a MoS\(_2\)-to-HfO\(_2\) barrier magnitude of about \(1.7\) eV and a floating-gate electron well depth magnitude of about \(2.1\) eV [1303.4799].

These two mechanisms are related but not identical. In the HfO\(_2\) trap-layer device, storage is distributed across trap states in a dielectric. In the graphene floating-gate device, storage occurs on an isolated conductive node with a high density of states. Both convert stored charge into a threshold-voltage shift of a MoS\(_2\) transistor, but their retention limits, scaling rules, and sensitivity to interface parasitics differ.

## 4. Electrical characteristics and benchmarking

The few-layer dual-gate HfO\(_2\)-trap memory established the principal benchmark for conventional MoS\(_2\) charge-trap memory on arXiv. Its top-gated transfer curves showed a maximum on/off ratio higher than \(10^5\) and a field-effect mobility of approximately \(170\ \text{cm}^2\text{V}^{-1}\text{s}^{-1}\). A top-gate sweep from \(-26\) V to \(+26\) V and back at \(V_{BG}=0\) yielded a memory window of about \(20\) V. The back gate tuned this window from \(15.6\) V at \(V_{BG}=+35\) V to \(21\) V at \(V_{BG}=-35\) V, and tuned the program/erase current ratio from about \(3\) to about \(10^4\). The same device family showed six different current levels and at least \(2\)-bit storage in one device [1407.7432].

Pulse studies in that architecture used \(+26\) V programming and \(-26\) V erasing, with pulse widths from \(1\) ms to \(3\) s for dynamic threshold-shift analysis and \(200\) ms for endurance cycling. The extracted stored electron density was approximately \(8.6\times10^{13}\ \text{cm}^{-2}\), the stored hole density approximately \(1.9\times10^{14}\ \text{cm}^{-2}\), and the charge-trapping rate varied from about \(10^{19}\) to \(10^{14}\ \text{cm}^{-2}\text{s}^{-1}\) as pulse width increased from \(1\) ms to \(3\) s. The threshold shift in retention experiments decreased from \(7.5\) V to \(6.4\) V after \(10^4\) s, leading to a projected charge loss of about \(28\%\) after \(10\) years, while endurance was demonstrated over \(120\) cycles [1407.7432].

The fully 2D monolayer MoS\(_2\)/graphene memory reported a maximum threshold shift or memory window of about \(8\) V for control-gate sweeps up to about \(+18\) V, a program/erase current ratio greater than \(10^4\), and a stored electron density of about \(3.7\times10^{13}\ \text{cm}^{-2}\). Dynamic switching was shown with \(\pm18\) V, \(100\) ms pulses at \(V_{ds}=50\) mV, endurance exceeded \(120\) cycles, and extrapolation from the threshold-voltage decay suggested that about \(30\%\) of the initial stored charge would remain on the floating gate after \(10\) years [1303.4799].

A later benchmark from the transferable black-phosphorus AHA stack sharpened the comparative context. That study reported a memory window exceeding \(12\) V from \(\pm18\) V sweeps, projected \(25\)–\(30\%\) charge loss after \(10\) years, and explicitly stated that the compared MoS\(_2\) flash memory showed \(70\%\) loss after \(10\) years. Its broader relevance lies less in the black-phosphorus channel than in the demonstration that a thin Al\(_2\)O\(_3\) tunnel oxide plus HfO\(_2\) trap layer can support large windows and strong retention in a 2D memory geometry [1511.07619].

## 5. Boundary cases and related MoS\(_2\) memory phenomena

Not every nonvolatile or hysteretic MoS\(_2\) device is a charge-trap memory in the strict sense. The surrounding literature contains several adjacent mechanisms that either mimic charge-trap memory or illuminate its failure modes.

| Class | Representative papers | Distinguishing storage variable |
|---|---|---|
| Conventional charge-storage transistor memory | [1407.7432], [1303.4799] | HfO\(_2\) trap occupancy or isolated floating-gate charge |
| Persistent optoelectronic / photodoping memory | [1309.1455], [2006.09986] | Long-lived charge separation or trapped interfacial charge written optically |
| Defect- or ion-mediated memory | [2306.04493], [2305.02259], [2601.16526] | Oxide traps, Na\(^+\) migration in SiO\(_2\), or mobile oxygen vacancies in HfO\(_2\) |
| Memristive resistive switching | [1504.01416], [1802.07785] | Grain-boundary or sulfur-vacancy redistribution and contact-barrier modulation |
| Volatile capacitor memory | [1912.07873] | Charge on an explicit storage capacitor, with MoS\(_2\) only as access transistor |

Graphene/MoS\(_2\) persistent photoconductivity memory demonstrated an optically written, electrically erased state with essentially no measurable decay over three decades in time at low photoexcitation intensity, stability over more than \(10\) hours, and rewriteability over days with better than \(95\%\) accuracy, but it had no tunnel oxide, no blocking oxide, and no engineered trap layer; the state was attributed to localized holes in MoS\(_2\) sustaining excess electrons in graphene [1309.1455]. A different MoS\(_2\)/BN/graphite photomemory shifted the threshold from about \(-2.2\) V to about \(-9.8\) V, extracted \(\Delta n_{ph}\approx 6\times10^{12}\ \text{cm}^{-2}\), achieved \(I_{ON}/I_{OFF}\) up to \(10^6\) at negative read gate bias, and extrapolated about \(50\%\) photocurrent retention after \(10\) years, but it attributed storage to trapped holes at the graphite/BN interface and required optical excitation for both write and erase [2006.09986].

Defect-engineered back-gated MoS\(_2\) FETs can also act as memory without a dedicated storage layer. Xe\(^{30+}\) irradiation at \(180\) keV converted nearly non-hysteretic monolayer MoS\(_2\)/SiO\(_2\) transistors into long-relaxation hysteretic memories; the hysteresis height increased linearly with ion fluence, the current hysteresis reached about two orders of magnitude at the highest fluence, and transient fits gave \(\tau_1=1600\) s and \(\tau_2=90\) s, with the active storage medium interpreted mainly as negatively charged irradiation-induced oxide defects in SiO\(_2\) [2306.04493]. In another direction, thermally driven monolayer MoS\(_2\)/SiO\(_2\)/Si mem-transistors grown by NaCl-assisted CVD showed weak clockwise hysteresis below room temperature but anti-clockwise hysteresis and multilevel nonvolatile states above about \(350\) K; at \(450\) K, \(R_1/R_0\) reached \(3.57\), the READ/RESET ratio reached about \(220\), and distinct levels remained discernible for \(1500\) s, with the mechanism assigned to gate-field-modulated Na\(^+\)-ion dynamics and charge transfer at the MoS\(_2\)/dielectric interface [2305.02259].

Memristive MoS\(_2\) devices form a separate branch. Grain-boundary-mediated monolayer devices showed switching ratios up to \(1000\) with gate-tunable set voltage, while later polycrystalline monolayer memristors showed switching ratios up to about \(500\) and threshold-voltage shifts of about \(10\)–\(20\) V, but both works treated the internal state primarily as vacancy migration, grain-boundary dynamics, or contact-barrier modulation rather than storage in a dedicated trap medium [1504.01416, 1802.07785]. By contrast, dual-gated MoS\(_2\) DRAM used a \(1\)T\(1\)C architecture with a storage capacitor and achieved \(1260\) ms retention by suppressing access-transistor leakage; its memory state was capacitor charge, not trapped charge in MoS\(_2\) or its gate dielectric [1912.07873].

## 6. Methodological issues, misconceptions, and design directions

A persistent misconception in the MoS\(_2\) memory literature is to equate transfer-curve hysteresis with intentional charge-trap memory. Pulse-based and environment-controlled measurements show why that inference is unreliable. In salt-assisted CVD monolayer MoS\(_2\) FETs on \(300\) nm SiO\(_2\), hysteresis in air reached about \(21\) V for a \(-20\) to \(35\) V sweep, but high vacuum reduced it by about \(95\%\); amplitude-sweep pulse \(I\)–\(V\) measurements with \(0.5\) ms pulses yielded essentially hysteresis-free transfer characteristics and increased the apparent mobility from \(15.13\) to \(30.65\ \text{cm}^2\text{V}^{-1}\text{s}^{-1}\), while single-pulse transients separated a fast trapping component with \(\tau_1=2.6\)–\(3.2\times10^{-4}\) s from a slow component with \(\tau_2=1.0\times10^{-2}\)–\(2.6\times10^{-2}\) s [2010.02052].

High-bias transport studies further show that MoS\(_2\) itself can be an unintended trap reservoir. Short-channel monolayer devices on \(285\) nm SiO\(_2\) exhibited trap-assisted space-charge-limited current with an exponential trap distribution,
\[
h(E)=\frac{N_t}{k_B T_c} e^{-E/k_B T_c},
\qquad
I \propto V^m,\quad m=\frac{T_c}{T}+1,
\]
and a temperature-independent critical voltage
\[
V_c=\frac{qN_tL^2}{2\varepsilon_0 \varepsilon_r},
\]
from which the trap density was extracted as about \(1.5\times10^{17}\) to \(2.3\times10^{17}\ \text{cm}^{-3}\) [1308.4858]. This implies that a measured memory window in a MoS\(_2\) transistor can include contributions from channel-localized traps, not only from an intended storage layer.

At the dielectric level, HfO\(_2\) and Al\(_2\)O\(_3\) diverge sharply under stress and temperature. Similar back-gated monolayer MoS\(_2\) FETs with about \(20\) nm HfO\(_2\) or Al\(_2\)O\(_3\) both showed sizeable clockwise hysteresis at room temperature, but at \(175^\circ\)C the HfO\(_2\) devices developed dominant counterclockwise hysteresis, negative \(V_{th}\) shift, self-doping, and negative differential resistance, which a compact model attributed to mobile positively charged oxygen vacancies drifting in HfO\(_2\). Al\(_2\)O\(_3\) devices displayed only minor counterclockwise dynamics even at \(275^\circ\)C. The study explicitly framed this as an insulator-selection paradigm: Al\(_2\)O\(_3\) is better suited to suppress detrimental negative \(V_{th}\) shifts in MoS\(_2\) logic FETs at high temperatures, whereas HfO\(_2\) can serve as an active memory layer that exploits these abnormal instabilities [2601.16526].

A plausible implication is that MoS\(_2\) charge-trap memory research is organized around a recurring balance. On one side is the deliberate use of high-\(k\) stacks, floating gates, or engineered interfaces to obtain large memory windows, strong retention, and multilevel states. On the other is the need to exclude parasitic storage in adsorbates, channel traps, substrate oxide traps, mobile ions, or grain-boundary defect networks. The most robust results in the literature therefore combine architectural control of the storage medium with diagnostics that discriminate intentional nonvolatile storage from transient or defect-mediated hysteresis.

Source: https://www.emergentmind.com/topics/mos-charge-trap-memory