---
title: 'MicroBCI: Low-Cost Shield-Based BCI'
url: https://www.emergentmind.com/topics/microbci
type: topic
---

# MicroBCI: Low-Cost Shield-Based BCI

MicroBCI is a low-cost shield-based brain–computer interface built around the STM32 Nucleo-55RG development board, designed to record EEG, EMG, and ECG signals across 8 channels through an ADS1299 biopotential analog front end and to stream or preprocess these data in real time [2509.16229]. In its reference form, it is an instrumentation and prototyping platform rather than a fully self-contained multi-class decoder: the published firmware implements digital filtering, artifact handling, and alpha-wave detection, while leaving more complex machine-learning inference to external host-side integration. The platform is presented as an accessible pathway into neuroscience and as a reproducible basis for applied research, especially where low cost, open hardware, and direct control over acquisition and preprocessing are primary requirements.

## 1. Definition, scope, and terminology

In the literature, MicroBCI denotes a specific hardware–firmware system in which a custom shield plugs directly into an STM32 Nucleo-55RG board, turning the board into a brain–computer interface capable of recording EEG, EMG, and ECG over 8 channels [2509.16229]. The core signal chain is explicit: electrodes feed an ADS1299 AFE providing low-noise amplification, programmable gain, and 24-bit $\Delta\Sigma$ conversion; the STM32 performs data buffering and digital signal processing; USB-CDC provides real-time transfer to a host PC.

The scope of the published system is narrower than that of many end-to-end BCI papers. The reference firmware performs bandpass and notch filtering, artifact detection, and alpha-band power estimation via Welch’s method, followed by threshold-based alpha-wave detection. No complex machine-learning classifiers are implemented in the reference firmware; the open-source design instead allows integration of external ML models such as SVM or CNN on a host PC [2509.16229]. This distinction is central for interpreting the term correctly: MicroBCI, in this usage, is primarily a low-cost, low-noise acquisition and preprocessing platform.

A common misconception is to treat all compact BCIs as equivalent. The STM32-based MicroBCI is an 8-channel acquisition shield with host-connected streaming and simple on-board detection, whereas other compact systems in the same general design space may execute the complete decoding pipeline locally. This difference matters for latency budgeting, power budgeting, software partitioning, and the feasibility of deploying specific paradigms such as SSVEP or multi-class motor imagery.

## 2. Hardware architecture and electrical design

The hardware is organized around an STM32 Nucleo-55RG development board, based on a Cortex-M0+ running at 48 MHz, with a shield that integrates the analog front end, power regulation, protection, and electrode interfacing [2509.16229]. The shield is powered only from a 5 V battery through an on-board 5 V input header, and on-board LDOs generate 3.3 V for digital logic and $\pm 2.5$ V analog supplies for the ADS1299. Communication between the ADS1299 and STM32 occurs over SPI at up to 10 MHz, while real-time data streaming to a host PC uses USB-CDC.

| Subsystem | Specification | Function |
|---|---|---|
| Core platform | STM32 Nucleo-55RG, Cortex-M0+, 48 MHz | Data buffering and digital signal processing |
| Analog front end | ADS1299IPAG, 8-channel biopotential AFE | Low-noise amplification, PGA, 24-bit $\Delta\Sigma$-ADC |
| Electrodes | Dry Ag/AgCl, 10 mm disc | EEG acquisition with separate reference and bias |
| Power | 5 V battery, 3.3 V and $\pm 2.5$ V rails | Isolated supply for digital and analog sections |
| Host interface | SPI up to 10 MHz; USB-CDC | Acquisition and real-time streaming |

The published bill of materials identifies a custom MicroBCI shield PCB, eight dry Ag/AgCl EEG electrodes, a 10-pin right-angle header, a $2 \times 5$ SPI ribbon cable, a JST B5B-EHS power header, LD3985M33R and TPS70925 regulators, 0603 passives, and PESD5V ESD diodes [2509.16229]. The electrode connector exposes eight channels plus separate reference and bias (DRIVE) connections.

The circuit overview emphasizes conventional mixed-signal design constraints. Each ADS1299 channel is tied to an electrode input followed by a $0.1\ \mu\text{F}$ coupling capacitor into the ADS1299 input multiplexer. On-board passive RC anti-aliasing is implemented as a 4th-order Butterworth stage before the ADC, with $R = 10\ \text{k}\Omega$ and $C = 4\ \text{nF}$, and the ground plane is split into analog and digital sections tied at a single star point near the ADC [2509.16229]. This arrangement is consistent with the device’s stated focus on low-noise EEG acquisition.

Key electrical parameters are likewise explicit. The ADC resolution is 24 bits, the programmable gain settings are $\{1,2,4,6,12,24\}$ with standard operation at $6\times$, the sampling rate is 250 samples/sec per channel with configurability to 128, 500, and 1 kS/s, and the input impedance exceeds $1\ \text{G}\Omega$ according to the ADS1299 datasheet [2509.16229].

## 3. Signal acquisition, montage, and conditioning

MicroBCI uses dry Ag/AgCl electrodes with 10 mm diameter and no gel requirement, with reported impedance in the range $200\ \text{k}\Omega$ to $5\ \text{M}\Omega$ [2509.16229]. The 8-channel montage follows the International 10–20 system:

- CH1 $\rightarrow$ F7
- CH2 $\rightarrow$ Fz
- CH3 $\rightarrow$ F8
- CH4 $\rightarrow$ C3
- CH5 $\rightarrow$ C4
- CH6 $\rightarrow$ T5 (P7)
- CH7 $\rightarrow$ Pz
- CH8 $\rightarrow$ T6 (P8)

Reference and bias electrodes are placed on the mastoid or earlobe. The selected montage supports frontal, central, temporal, and parietal coverage rather than dense sensorimotor localization alone, which is consistent with the platform’s characterization as a general-purpose biopotential interface.

The analog and digital filters are specified analytically. The passive anti-aliasing stage is a 4th-order Butterworth low-pass with cutoff $f_c \approx 125\ \text{Hz}$:

$$
H_{LP}(s) = \frac{\omega_c^4}{s^4 + 2.613\omega_c s^3 + 3.414\omega_c^2 s^2 + 2.613\omega_c^3 s + \omega_c^4},
$$

where $\omega_c = 2\pi \times 125\ {\rm rad/s}$ [2509.16229].

Digital bandpass filtering in firmware uses cascaded IIR stages to form a 1–40 Hz bandpass:

$$
H_{BP}(s) = H_{HP}(s)\cdot H_{LP}(s),
$$

$$
H_{HP}(s) = \frac{s^2}{s^2 + \sqrt{2}\,\omega_L s + \omega_L^2},
$$

where $\omega_L = 2\pi\cdot1\ {\rm rad/s}$ [2509.16229].

Mains rejection is provided by a 50 Hz notch filter:

$$
H_{notch}(s) = \frac{s^2 + \omega_0^2}{s^2 + \frac{\omega_0}{Q} s + \omega_0^2},
$$

with $\omega_0 = 2\pi\cdot50\ {\rm rad/s}$ and $Q \approx 35$ [2509.16229].

The platform’s reported noise characteristics are framed relative to alpha-band sensing. The measured input-referred noise over 0.5–100 Hz is $V_{n,\mathrm{rms}} \approx 1\ \mu\text{V}$, while typical alpha signal amplitude is stated as $A_{\mathrm{signal}} = 35$–$65\ \mu\text{V}$ [2509.16229]. Using the band SNR definition

$$
\mathrm{SNR} = 20\cdot \log_{10}(A_{\mathrm{signal}}/V_{n,\mathrm{rms}}),
$$

the report gives

$$
20\cdot \log_{10}(50\ \mu\text{V}/1\ \mu\text{V}) \approx 34\ \text{dB}.
$$

The same section states that the quantitative noise floor was validated against ADS1299 reference performance [2509.16229]. In practical terms, this positions MicroBCI as adequate for alpha-rhythm studies and for prototyping algorithms that require stable low-frequency EEG structure.

## 4. Firmware, data path, and on-board processing

The firmware runs on the STM32 Nucleo-55RG and uses a simple round-robin scheduler to organize real-time acquisition and preprocessing [2509.16229]. The published task structure is:

1. SPI read of ADS1299 data at 250 Hz using DMA.
2. Circular buffer management for storing raw samples.
3. Digital preprocessing, including filtering and artifact detection.
4. USB-CDC transmission of processed or raw data packets.

The memory budget is stated as 64 kB SRAM for double buffering with 32-bit words, and the communication stack uses SPI1 at up to 10 MHz with 16-bit frames and USB-CDC at 115 200 bps, configurable as needed [2509.16229]. This is a modest resource envelope compared with desktop-oriented BCI pipelines.

The digital signal-processing pipeline is intentionally simple and explicit. First, the data are passed through a real-time 1–40 Hz 4th-order IIR bandpass. Second, a 50 Hz 2nd-order IIR notch is applied. Third, artifact removal is performed by thresholding high-pass ($>70\ \text{Hz}$) energy to detect muscle artifacts, followed by zero-phase notch interpolation. Fourth, alpha-band power is computed via Welch’s method on 1 s windows with 50% overlap. The discrete Fourier transform and PSD expressions are given as [2509.16229]

$$
X[k] = \sum_{n=0}^{N-1} x[n] \, e^{-j\,2\pi\,k\,n / N},\quad k=0,\dots,N-1,
$$

and

$$
P_{xx}(f_k) = \frac{1}{N\,U}\,\bigl|X[k]\bigr|^2,\quad U = \frac{1}{N}\sum_{n=0}^{N-1} w[n]^2,
$$

where $w[n]$ is the analysis window, for example Hanning. Finally, alpha-wave detection is implemented by comparing $P_{xx}$ in the 8–12 Hz band to a calibrated threshold.

The absence of an embedded multi-class classifier is deliberate rather than accidental. The reference firmware performs alpha detection by simple thresholding on bandpower, and the report explicitly states that no complex machine-learning classifiers are implemented on board [2509.16229]. This creates a clean separation between acquisition/preprocessing and higher-level decoding. A plausible implication is that MicroBCI is well suited to experimental workflows in which raw or lightly processed data are sent to a host for rapid iteration on classifiers without repeated firmware redesign.

The data interfaces are also formalized. USB-CDC frames use the structure `[Header=0xA5][Timestamp (4 bytes)][Ch1…Ch8 float32][Checksum (1 byte)]`, and host-side CSV export follows the format `"t_ms,Ch1,Ch2,…,Ch8\n"` [2509.16229]. These details matter for synchronized logging, interoperability, and reproducibility across lab software stacks.

## 5. Validation, performance, and reproducibility

Experimental validation in the MicroBCI report focuses on alpha-wave detection rather than on a generic BCI benchmark [2509.16229]. The protocol involved healthy volunteers $(n = 3)$ aged 22–28 with mixed gender, a single-channel test at Fz (Ch2) with reference on the mastoid, and eyes-closed versus eyes-open recording conditions. Trials lasted 8 s and were repeated 5 times per state, with sampling at 250 Hz and an 8–12 Hz bandpass.

The reported quantitative results are specific. Closed-eyes alpha amplitude was $45 \pm 10\ \mu\text{V}$ RMS, open-eyes alpha amplitude was $12 \pm 5\ \mu\text{V}$ RMS, and detection accuracy for closed versus open states using a bandpower threshold yielded sensitivity of 92% and specificity of 90% [2509.16229]. The threshold was calibrated midway between the mean open and closed RMS values. These metrics support the claim that the platform effectively detects alpha brain waves.

The comparative benchmark is restrained. The report states that MicroBCI performance closely matches commercial ADS1299-based systems, citing published noise floors of approximately $0.7\ \mu\text{V}_{\mathrm{rms}}$ and alpha SNR around 36 dB [2509.16229]. Given the measured $V_{n,\mathrm{rms}} \approx 1\ \mu\text{V}$ and computed alpha-band SNR near 34 dB, the comparison is presented as a proximity claim rather than parity.

Reproducibility is a defining feature of the platform. The hardware files, schematics, firmware, and example datasets are made available through a GitHub repository, and the report includes explicit assembly and deployment instructions: mount the shield on the STM32 Nucleo-55RG, solder SMT passives and ADS1299, populate connectors, connect a 5 V USB power bank, and attach electrodes according to the 10–20 montage [2509.16229]. Firmware deployment is described through STM32CubeIDE and ST-Link, and extension guidance includes cascading a second ADS1299 for additional channels, integrating CMSIS-DSP FFT routines for on-board PSD, and building Python or Matlab host drivers via pySerial. In encyclopedia terms, MicroBCI is therefore notable not only for cost and performance, but also for explicit reproducibility at the hardware, firmware, and data-format levels.

## 6. Position within compact and embedded BCI research

MicroBCI occupies one point in a broader landscape of compact BCIs that trade off power, autonomy, modality, and computational complexity. A closely related embedded system is EdgeSSVEP, a fully embedded microcontroller-based SSVEP BCI platform that performs real-time EEG acquisition, zero-phase filtering, and on-device classification within a low-power 240 MHz ESP32-S3 MCU operating at 222.4 mW in normal mode at 240 MHz [2601.01772]. EdgeSSVEP uses an 8-channel ADS1299 front end, a 3-axis LIS3DH accelerometer for head-motion artifact detection, a zero-phase third-order Butterworth bandpass from 2 Hz to 45 Hz applied by forward–backward IIR filtering, and CCA-based SSVEP classification over six stimulus frequencies $\{7,7.5,8,8.5,9,11\ \text{Hz}\}$ [2601.01772]. With 10 participants and 24 trials each, it reports $99.17\% \pm 1.76\%$ accuracy, $27.33$ bits/min ITR, and total processing latency of $488.03 \pm 2.70$ ms. Relative to MicroBCI, the contrast is sharp: EdgeSSVEP eliminates dependence on PC-based processing, whereas MicroBCI’s reference implementation emphasizes acquisition, preprocessing, and host-connected analysis.

A second adjacent line of work uses the term “MicroBCI” in a more methodological sense, centered on command expansion from a small set of motor-imagery primitives. Korhan et al. describe a compact BCI approach in which four simple motor imageries—left hand, right hand, tongue, and feet—are combined in pairs to generate up to ten commands [2105.14493]. The underlying assumption is that the EEG induced by dual imagination is approximately the linear sum of the component simple imageries, formalized as

$$
X_{ab}(k,n)=\frac{1}{2}\Bigl[X_a(k,n)+X_b(k,n)\Bigr].
$$

This produces six synthetic combined classes in addition to the four simple classes. Classification is performed by the small-sized CNN DivFE, a Divergence-based Feature Extractor using seven successive 1D convolutional layers, Walsh-vector targets of rank $M=16$, MSE loss, and a minimum-distance decision rule [2105.14493]. The study reports an average classification performance of 81.8% for ten classes across BCI Competition III and IV datasets, and 76.5% success for combined MI EEG acquired in real time. It also states that total BCI command latency, including filtering, epoch windowing, and DivFE inference, can be kept under 200 ms, with a model size of roughly 4 million parameters and a typical memory footprint of approximately 15 MB [2105.14493].

Taken together, these systems delineate three distinct meanings often compressed under the idea of a “micro” BCI. MicroBCI in the STM32 sense is a low-cost 8-channel measurement and preprocessing shield [2509.16229]. EdgeSSVEP represents a fully embedded, low-power, on-device decoder for SSVEP [2601.01772]. The motor-imagery command-expansion work shows how a compact task set can support ten commands when paired with a small CNN and synthetic class generation [2105.14493]. This suggests that “MicroBCI” is best understood not as a single architecture, but as a family of resource-constrained BCI designs spanning acquisition hardware, embedded inference, and compact control paradigms.

## 7. Significance and limitations

The principal significance of MicroBCI lies in the combination of low-cost hardware, low-noise 8-channel acquisition, explicit firmware architecture, and open reproducibility [2509.16229]. Its use of the ADS1299 places it within a technically mature EEG front-end lineage, while the STM32 Nucleo-55RG and shield format make the system accessible for rapid prototyping, education, and algorithm development. Because the platform can record EEG, EMG, and ECG, it is not restricted to a single neurophysiological use case.

Its limitations are equally explicit. The validation protocol is based on alpha-wave detection in $n = 3$ healthy volunteers, with single-channel testing at Fz and a binary condition contrast of eyes-closed versus eyes-open [2509.16229]. No multi-class BCI benchmark, no on-device deep-learning classifier, and no standalone assistive-control demonstration are reported in the reference implementation. For researchers seeking a fully autonomous embedded decoder, EdgeSSVEP provides the closer exemplar; for those seeking expanded command vocabularies from motor imagery, the DivFE-based ten-command framework is the more directly relevant comparator [2601.01772; 2105.14493].

Within those bounds, MicroBCI serves as a well-specified and reproducible substrate for experimentation. A plausible implication is that its most important role is infrastructural: it reduces the barrier to acquiring reasonably clean 8-channel biopotential data on a battery-powered embedded platform, after which paradigm-specific decoding—whether alpha-thresholding, SSVEP classification, or motor-imagery recognition—can be layered on top according to the computational budget and research objective.

Source: https://www.emergentmind.com/topics/microbci