---
title: 'Memory Quadruple: Fourfold Memory Concept'
url: https://www.emergentmind.com/topics/memory-quadruple
type: topic
---

# Memory Quadruple: Fourfold Memory Concept

Searching arXiv for the cited papers and topic context.
arxiv_search.query({"search_query":"id:2410.20332 OR id:2407.20628 OR id:1007.1664","start":0,"max_results":10})
arxiv_search.query({"search_query":"all:\"memory quadruple\" OR all:\"four quantum memories\" OR all:\"quad-port memory\" OR all:\"4 bits per cell RRAM\"","start":0,"max_results":10})
In current research usage, a memory quadruple is most naturally understood as a fourfold organization of memory resources rather than as a single canonical device class. The idea appears in substantially different technical regimes: as four spatially separated quantum memories that store a heralded quadripartite spin-wave state, as a pseudo-quad-port SRAM architecture that time-multiplexes a standard 6T array to provide 1-port, 2-port, 3-port, or 4-port access configurations, and as a broader fourfold storage limit in open-loop RRAM, where information-theoretic analysis places the maximum reliable capacity around 4 bits per cell under common conductance ranges and variations [1007.1664] [2407.20628] [2410.20332].

## 1. Scope of the term

The fourfold structure captured by the phrase takes different meanings depending on the memory technology. In quantum networking, it refers to four atomic memories sharing one delocalized excitation. In SRAM architecture, it refers to four logical ports implemented around a single conventional macro. In resistive memory, it refers not to four separate memories but to a practical upper bound of roughly four bits in one cell under open-loop programming.

| Research setting | Fourfold structure | Primary result |
|---|---|---|
| Cold-atom quantum memory | Four atomic ensembles \(a,b,c,d\) | Genuine 4-partite entanglement stored and transferred to four photonic channels |
| 6T SRAM architecture | 1-port, 2-port, 3-port, 4-port configurability | 4× bandwidth with 8% wrapper overhead |
| Open-loop RRAM | Around 4 bits per cell | Capacity saturates near 4 bits under common \(\Delta G\) and \(\sigma\) |

These uses are technically distinct. A memory quadruple in the first case concerns multipartite entanglement and coherent matter-light transfer; in the second, access multiplicity and bandwidth; in the third, the count of reliably distinguishable storage states. This suggests that the term functions as a descriptive umbrella for fourfold memory organization rather than a standardized taxonomy.

## 2. Quadripartite quantum-memory realization

Choi et al. realize a four-memory system using four spatially separated cold-atom ensembles of Cs atoms, each containing approximately \(10^6\) atoms, prepared in \(|g\rangle \equiv 6S_{1/2}, F=4\), with \(|s\rangle \equiv 6S_{1/2}, F=3\) as the storage state and \(|e\rangle \equiv 6P_{3/2}, F'=4\) as the excited state for Raman processes [1007.1664]. The ensembles, labeled \(\epsilon=a,b,c,d\), are located in a single vacuum chamber at the corners of a square with approximately \(1\ \mathrm{mm}\) separation. Write and read beams at an angle \(\theta \approx 2.5^\circ\) relative to each emission mode define four distinct spin-wave modes,
\[
|\overline{s}_{\epsilon}\rangle = \frac{1}{\sqrt{N_{a,\epsilon}}} \sum_{i=1}^{N_{a,\epsilon}} e^{i\delta k \cdot r_i}|g\ldots s_i \ldots g\rangle_{\epsilon}.
\]

The entanglement protocol is measurement-induced. A single write pulse of \(20\ \mathrm{ns}\), red detuned by \(\Delta = +10\ \mathrm{MHz}\) from \(|g\rangle \to |e\rangle\), is split equally into four beams and applied simultaneously to ensembles \(a,b,c,d\). Each ensemble may scatter a single Raman photon into its mode \(\gamma_{1,\epsilon}\). The four output modes \(\gamma_1=\{a_1,b_1,c_1,d_1\}\) interfere on a four-port fiber interferometer with actively stabilized relative path-length phases. A click at the single-photon detector \(D_h\) projects one collective excitation delocalized over the four ensembles, erasing which-path information and preparing the ideal quadripartite atomic \(W\) state
\[
|W\rangle_A=\frac{1}{2}\Big[
|\overline{s}_a,\overline{g}_b,\overline{g}_c,\overline{g}_d\rangle
+e^{i\phi_1}|\overline{g}_a,\overline{s}_b,\overline{g}_c,\overline{g}_d\rangle
+e^{i\phi_2}|\overline{g}_a,\overline{g}_b,\overline{s}_c,\overline{g}_d\rangle
+e^{i\phi_3}|\overline{g}_a,\overline{g}_b,\overline{g}_c,\overline{s}_d\rangle
\Big].
\]

The heralding probability per clock cycle is \(p_h \approx 3\times 10^{-4}\), corresponding to an excitation probability \(\xi \approx 5\times 10^{-3}\). After heralding, the four ensembles store the spin-wave state for a programmable delay \(\tau\). The implementation is therefore a memory quadruple in the most literal sense: four distinct quantum memories jointly encode a single multipartite resource state.

## 3. Readout, verification, and entanglement certification

Readout is performed with a strong read pulse of \(20\ \mathrm{ns}\), resonant with \(|s\rangle \to |e\rangle\), with Rabi frequency approximately \(24\ \mathrm{MHz}\). Under the same phase-matching conditions, each stored spin-wave is converted back into a single photon in mode \(\gamma_{2,\epsilon}=\{a_2,b_2,c_2,d_2\}\) with measured single-photon retrieval efficiency \(\eta_{\mathrm{read}} = 0.38 \pm 0.06\). Collectively, the local unitary \(\hat U_{\mathrm{read}}\) maps the atomic \(W\) state to the photonic state
\[
|W\rangle_\gamma=\frac{1}{2}\Big[|1000\rangle + e^{i\phi'_1}|0100\rangle + e^{i\phi'_2}|0010\rangle + e^{i\phi'_3}|0001\rangle\Big]
\]
[1007.1664].

Because background and higher-order Raman processes can introduce zero or multiple excitations, the readout state is written as
\[
\rho_r = p_0\rho_0 + p_1\rho_1 + p_{\ge 2}\rho_{\ge 2}.
\]
Two quantities are then used for certification. The first is the normalized multiple-excitation contamination,
\[
y_c \equiv \frac{8}{3}\frac{p_{\ge 2}p_0}{p_1^2},
\]
which ranges from \(y_c=0\) for perfect single excitation to \(y_c=1\) for a balanced coherent state. The second is the sum-uncertainty
\[
\Delta \equiv \sum_{i=1}^4 \left(\langle (\Pi_i^{(c)})^2\rangle - \langle \Pi_i^{(c)}\rangle^2\right),
\]
measured with a second four-port verification interferometer having actively stabilized internal phases \(\{\beta_1,\beta_2,\beta_3\}\). Ideal one-photon \(W\)-states give \(\Delta=0\), whereas a fully incoherent mixture gives \(\Delta=3/4\).

The nonlinear witness is defined through bounds \(\Delta_b^{(M-1)}(y_c)\). For \(N=4\) modes, \(\Delta < \Delta_b^{(3)}(y_c)\) certifies genuine 4-partite entanglement, \(\Delta < \Delta_b^{(2)}(y_c)\) certifies at least 3-partite entanglement, and \(\Delta < \Delta_b^{(1)}(y_c)\) certifies at least bipartite entanglement. At low \(y_c\), the numerical bounds are approximately \(\Delta_b^{(3)}(y_c\approx 0)\approx 0.19\), \(\Delta_b^{(2)}(y_c\approx 0)\approx 0.38\), and \(\Delta_b^{(1)}(y_c\approx 0)\approx 0.70\). At the optimal operating point \(\xi \approx 5\times 10^{-3}\), the reported values are
\[
y_c^{\min} = 0.038 \pm 0.006,\qquad
\Delta^{\min} = 0.07^{+0.01}_{-0.02}.
\]
Since \(\Delta^{\min} < \Delta_b^{(3)}(y_c^{\min}) = 0.19^{+0.05}_{-0.01}\), the experiment certifies genuine quadripartite entanglement with \(>10\sigma\) significance.

A lower bound on the stored atomic fidelity is obtained from
\[
\tilde F^{(A)} \ge \tilde p_1 \cdot \left[\sqrt{\frac{1}{2}\left(\frac{1}{2}-\Delta\right)}+\frac{1}{2}\right].
\]
Using \(\Delta^{\min}\), \(\tilde p_1 \approx p_1/(p_1+p_{\ge2})\), and \(\eta_{\mathrm{read}}=0.38\), the inferred atomic fidelity is \(\tilde F^{(A)}=0.9\pm 0.1\). After readout, the photonic fidelity is \(\tilde F^{(\gamma)} \approx 0.35 \pm 0.02\), and the overall matter-light entanglement transfer is \(\lambda \approx 0.39 \pm 0.04\). Decoherence is dominated by motional dephasing with \(v_d \approx 14\ \mathrm{cm/s}\), yielding a memory time \(\tau_m = 1/(|\delta k|v_d)\approx 17\ \mu\mathrm{s}\). The coherence boundaries are crossed at approximately \(\tau_m^{(3)}\approx 15\ \mu\mathrm{s}\), \(\tau_m^{(2)}\approx 21\ \mu\mathrm{s}\), and \(\tau_m^{(1)}\approx 24\ \mu\mathrm{s}\), while storage is reported up to \(36\ \mu\mathrm{s}\).

## 4. Pseudo-quad-port SRAM as a classical memory quadruple

A distinct meaning of memory quadruple appears in the pseudo-quad-port SRAM architecture of "Configurable Multi-Port Memory Architecture for High-Speed Data Communication" [2407.20628]. The design does not modify the 6T SRAM bitcell. Instead, it wraps a standard single-port array with input registers on ports \(A\)–\(D\), a 4-to-1 multiplexer on the address bus, a 4-to-1 multiplexer on the write-data bus, a 1-to-4 demultiplexer on the sense-amplifier outputs, a finite-state machine, a priority encoder, and a clock-generator that produces CLKP, BACK, and CLK2 pulses.

The operative feature is time multiplexing. On each external clock edge, CLKP latches all port inputs, BACK generates \(N\) positive pulses that assert the SRAM macro enable once per active port, and \(N-1\) CLK2 pulses advance the FSM so that the next port is selected. The number of enabled ports is \(N=\mathrm{popcount}(\mathrm{port\_en})\), and the block denoted “N-ports_en” feeds \((B_1,B_0)\) to the clock generator according to \(00\to 1\)-port, \(01\to 2\)-port, \(10\to 3\)-port, \(11\to 4\)-port. A single decoder, single write-driver pair, and single sense-amp array are reused across all enabled ports. The architecture is therefore explicitly pseudo-quad-port rather than a true replicated-port bitcell design.

The bandwidth scaling is given by
\[
B(N)=W \times N f_{\mathrm{CLK}},
\]
so that
\[
B(4)=4\,B(1).
\]
The same paper reports \(V_{DD}=1.2\ \mathrm{V}\), external \(f_{\mathrm{CLK}}=250\ \mathrm{MHz}\), and effective memory-access rate \(f_{\mathrm{MEM}}=1\ \mathrm{GHz}\) in 4-port mode. Assuming 64-bit words, the aggregate bandwidth is
\[
B(4)=64\ \text{bits} \times 1\times 10^9\ \text{Hz}=64\ \text{Gbit/s}.
\]
The macro size is \(16\ \mathrm{Kb}=2\ \mathrm{K}\times 8\ \text{bits}\), and the total macro area is \(0.085\ \mathrm{mm}^2\), including 8% wrapper overhead. The bare 6T array is approximately \(0.079\ \mathrm{mm}^2\), the wrapper approximately \(0.006\ \mathrm{mm}^2\), and the bitcell area approximately \(5.3\ \mu\mathrm{m}^2/\text{bit}\).

Area efficiency is compared against multi-port bitcell alternatives by defining \(A_0\) as the area per bit of the 6T cell. From Table IV, the 8T-2P cell area is approximately \(1.3A_0\) and the 12T-4P cell area approximately \(2.0A_0\), while the proposed 6T-wrapper solution keeps cell area at \(A_0\) plus 8% macro overhead. The resulting area-efficiency ratios are \(1.3\times\) relative to dual-port 8T and \(2.0\times\) relative to quad-port 12T. Dynamic power scales approximately linearly with the number of active pseudo-ports:
\[
P_{\mathrm{dyn},N}\approx N\cdot P_{\mathrm{dyn},1},
\]
while per-port average power remains \(P_{\mathrm{dyn},1}\), so per-port energy is unchanged.

A common misunderstanding is to equate this architecture with a true four-port SRAM cell. The paper’s own description makes the distinction clear: there is no duplication of the decoder, write drivers, or sense amplifiers; the wrapper simply reuses them \(N\) times per external clock. The “quadruple” therefore lies in effective access multiplicity and bandwidth, not in four simultaneous physically independent bitcell ports.

## 5. Four-bit open-loop RRAM and the limit of per-cell multiplicity

A third fourfold theme appears in open-loop written RRAM, where the relevant question is not four memories or four ports but whether one memory cell can reliably sustain approximately four bits of information [2410.20332]. The paper models open-loop write as an analog channel in which an input level \(V\) is mapped to an output conductance \(G\) with noise. The number of discrete levels \(N\) is the number of pre-defined conductance states, equivalently \(V\in\{v_1,\ldots,v_N\}\), each used with probability \(1/N\). The conductance range is \(\Delta G \approx G_{\max}-G_{\min}\), and the conductance variation \(\sigma\) is the standard deviation around each target level. The surveyed RRAMs span approximately \(1\ \mu\mathrm{S}\) to \(250\ \mu\mathrm{S}\), and experimentally \(\sigma\) typically lies in \([3\ \mu\mathrm{S},20\ \mu\mathrm{S}]\).

Under the simplifying assumptions of equal level spacing and Gaussian output distributions,
\[
p(G|V=v_i)=\frac{1}{\sigma\sqrt{2\pi}}\exp\!\left[-\frac{(G-G_i)^2}{2\sigma^2}\right],
\]
with
\[
G_i = G_{\min} + (i-1)\frac{\Delta G}{N-1},
\]
the mutual information is
\[
I(V;G)=H(V)-H(V|G).
\]
Because the levels are equiprobable, \(H(V)=\log_2 N\), and numerical evaluation yields the channel capacity \(C(N,\sigma,\Delta G)\). A rough approximation, based on an AWGN-channel analogy with nearest-neighbor overlap, gives
\[
N_{\max}\approx \frac{\Delta G}{c\,\sigma},\qquad
C_{\max}\approx \log_2\!\left[\frac{\Delta G}{c\,\sigma}\right],
\]
with \(c\approx 4\) in the paper’s detailed numerics.

The reported trade-off is explicit. For small \(N\), level overlap is negligible and \(C\approx \log_2 N\). As \(N\to N_T=q\cdot \Delta G/\sigma\), with \(q\approx 4\), adjacent Gaussians overlap significantly, the conditional entropy \(H(V|G)\) grows, and capacity saturates. For \(\Delta G\approx 249\ \mu\mathrm{S}\) and \(\sigma=3\ \mu\mathrm{S}\), the numerical curves show \(C_{\max}\approx 4.3\) bits once \(N\approx 2^4\) (\(=16\)–\(32\)); increasing \(N\) beyond approximately \(32\) yields less than 5% further gain. As \(\sigma\) increases, the maximum falls nonlinearly:
- \(\sigma=5\ \mu\mathrm{S}\to C_{\max}\approx 3.7\) bits
- \(\sigma=10\ \mu\mathrm{S}\to C_{\max}\approx 2.8\) bits
- \(\sigma=20\ \mu\mathrm{S}\to C_{\max}\approx 1.6\) bits

The assumptions are restrictive but clearly stated: open-loop writing only, no verify-and-correct steps, identical \(\sigma\) for every level, no signal-dependent noise, uniform spacing, equal use probability, and clipped Gaussian tails at the range edges. The paper argues that the absence of a comprehensive theoretical treatment has led to misleading conclusions that either exaggerate or underestimate RRAM storage capacity. Surveying published data together with the authors’ own HfO\(_2\) devices, it finds that \(\sigma\) almost always falls in \([3\ \mu\mathrm{S},20\ \mu\mathrm{S}]\) over \(\Delta G\lesssim 250\ \mu\mathrm{S}\), numerical integration of \(I(V;G)\) versus \(N\) saturates near 4 bits, and randomizing \(\sigma\) level to level lowers the average capacity below 3 bits. The conclusion is that, without verify/correct loops, the maximum practically achievable storage per RRAM cell is of order four bits.

## 6. Distinctions, limits, and recurrent misconceptions

The three research lines show that a fourfold memory designation can refer to fundamentally different quantities. In the quantum-memory case, the number four indexes the parties sharing a single delocalized spin-wave excitation. In pseudo-quad-port SRAM, it indexes the number of configurable logical access ports served within one external clock period. In open-loop RRAM, it indexes the approximate number of reliable bits that can be encoded in one noisy analog cell. Taken together, these works suggest that “quadruple” may describe count, access multiplicity, or capacity, depending on context.

Several misconceptions are addressed directly by the cited works. One is that easy programmability into multiple or quasi-continuous RRAM conductance states implies high reliable storage density; the information-theoretic analysis shows that conductance variation and overlap impose a practical ceiling near 4 bits in open-loop operation [2410.20332]. Another is that a pseudo-quad-port SRAM should be interpreted as a true quad-port cell; the architecture instead time-multiplexes a single decoder, write-driver pair, and sense-amp array, and the 4× bandwidth follows from \(f_{\mathrm{MEM}}=Nf_{\mathrm{CLK}}\), not from four independent physical ports [2407.20628]. A further misconception would be to treat the photonic readout of the four-memory quantum system as separate from the stored matter entanglement; because the mapping \(\hat U_{\mathrm{read}}\) is local, the measured photonic entanglement provides a rigorous lower bound on the stored atomic entanglement [1007.1664].

The broader significance of the memory quadruple concept is therefore not a single universal architecture but a recurring fourfold design objective under different physical constraints. In quantum networking, the operative problem is coherence and multipartite certification. In SRAM, it is bandwidth under area and power constraints. In RRAM, it is the information-theoretic limit imposed by analog variability. Each case turns a nominally simple factor of four into a quantitatively constrained engineering or physical statement.

Source: https://www.emergentmind.com/topics/memory-quadruple