---
title: Low-Power Synchronization Signal (LP-SS)
url: https://www.emergentmind.com/topics/low-power-synchronization-signal-lp-ss
type: topic
---

# Low-Power Synchronization Signal (LP-SS)

Searching arXiv for the cited LP-SS and related synchronization papers to ground the article in recent literature.
Low-Power Synchronization Signal (LP-SS) denotes a synchronization reference engineered for receivers that must preserve timing and measurement capability under strict energy constraints. In the standardized 5G-Advanced sense, LP-SS is the synchronization-and-measurement companion to the Low-Power Wake-Up Signal (LP-WUS) for user equipments operating in `RRC_IDLE` and `RRC_INACTIVE`, allowing a low-power receiver to maintain coarse synchronization and perform serving-cell measurements while the main radio remains switched off [2507.10207]. In a broader systems sense, the literature describes closely analogous mechanisms—periodic BLE synchronization packets, LPWAN chirp preambles, LoRa preambles, ambient cellular anchors for backscatter, and coherent-state clock signals—that serve the same functional role: they provide a low-cost timing anchor and measurement reference without sustaining a full-power receive chain [2309.14867] [2507.23029] [2502.08485] [2506.01743] [2606.08845].

## 1. Standardized role in 5G-Advanced Release 19

In 3GPP 5G-Advanced Release 19, LP-SS is introduced together with LP-WUS as part of a low-power idle and inactive mode architecture. The network configures the feature through RRC signaling, specifically via `lowPower-Config-r19` in `SIB1` within `DownlinkConfigCommonSIB`. The operational context is the conventional NR requirement that a UE in `RRC_IDLE` or `RRC_INACTIVE` periodically wakes during each DRX cycle to monitor paging and to perform mobility- and measurement-related tasks. The cited DRX cycle range is **320 ms to 2560 ms**, and the associated periodic main-radio activity keeps idle power consumption in the regime of tens of milliwatts [2507.10207].

Within that architecture, LP-WUS and LP-SS divide the idle-mode burden. LP-WUS is the trigger for paging reception, while LP-SS supplies the low-power receiver with the synchronization and measurement support required before paging can be decoded reliably. The formal motivation is that LP-WUS alone is insufficient: even if paging wake-up can be delegated to a low-power path, the UE still needs time/frequency alignment and cell-quality measurements. LP-SS therefore fills the gap between dormant main-radio operation and continued reachability. The paper states that the resulting architecture can enable power savings of **up to 80%** relative to conventional paging mechanisms [2507.10207].

A recurrent misconception is that LP-SS is simply a reduced-size version of the conventional synchronization signal block. The Release-19 description rejects that interpretation explicitly: LP-SS is designed for the low-power receiver path rather than the normal NR receiver chain, and its function is tied to wake-up-radio operation, measurement continuity, and coarse synchronization under main-radio-off conditions [2507.10207].

## 2. Signal structure, configurability, and measurement semantics

The physical-layer design of LP-SS follows the same low-power philosophy as LP-WUS. LP-SS is periodic with configurable periodicity of **320 ms or 160 ms**, a direct tradeoff between signaling overhead and tolerance to time/frequency drift. It spans **\(L_{LPSS}\in\{4,6,8\}\)** consecutive OFDM symbols within a slot, and there is **one LP-SS per configured beam**. Configuration further includes an offset relative to **SFN0** and one or two start symbols. In the example summarized in the literature, **\(L_{LPSS}=6\)**, the periodicity is **160 ms**, there are **four configured beams**, and there are **two LP-SS occasions per slot**, each corresponding to one beam [2507.10207].

Both LP-WUS and LP-SS use **On-Off Keying (OOK)** so that reception can be handled by a simple **energy detector (ED)** or envelope detector. That design choice is central: it removes the need for I/Q phase tracking in the low-power path and thereby lowers implementation complexity and power draw. For LP-SS specifically, the signal is defined through a binary sequence \(\mathbf{b}_{LPSS}\) selected according to three criteria: **measurement accuracy**, **synchronization accuracy**, and **good correlation properties**. One of four different LP-SS sequences can be configured per cell to reduce interference from neighboring cells. The parameterizations listed for shorter sequences are \(\{B_{LPSS},M_{LPSS},L_{LPSS}\}=\{6,1,6\}\), \(\{12,2,6\}\), and \(\{16,4,4\}\). These are balanced sequences, meaning that they contain an equal number of ones and zeros, which is stated to benefit measurement accuracy [2507.10207].

Each bit of \(\mathbf{b}_{LPSS}\) is mapped to an OFF OOK symbol when the bit is 0 and to an ON symbol when the bit is 1. The ON symbol is built from a cyclically extended Zadoff-Chu-style sequence using **\(n_{cs}=0\)** and a network-configured root \(q\). For the special case **\(M_{LPSS}=1\)**, the network may omit the root configuration, permitting an unspecified ON-sequence and even enabling reuse of legacy NR signals such as **PSS** or **TRS** on the OOK ON-symbols. This reuse is presented as a way to improve resource utilization and scheduling flexibility [2507.10207].

LP-SS is also a measurement signal. The Release-19 formulation defines serving-cell metrics including **LP-RSSI**, **LP-RSRP**, and **LP-RSRQ**. LP-RSSI is described as the linear average total received power across all LP-SS bits or symbols. LP-RSRP is the average received power restricted to the OOK ON-symbols only. LP-RSRQ is defined in words as the ratio of LP-RSRP to LP-RSSI, and because both are derived from the same signal, the paper notes that LP-RSRQ cannot exceed 1. This places LP-SS in continuity with conventional NR measurement semantics, but on a signal and receiver path specifically optimized for low-power idle behavior [2507.10207].

## 3. Receiver architecture and operating procedure

The LP-SS operating model presumes a split receiver architecture. The **low-power receiver (LR)** remains available while the **main radio (MR)** is switched off. In `RRC_IDLE` and `RRC_INACTIVE`, the LR monitors **LP-SS** for measurements and synchronization, and monitors **LP-WUS** to decide whether the MR must wake for paging decoding. The association between an **LP-WUS Occasion (LO)** and a **Paging Occasion (PO)** is anchored through signaling in `SIB1`, and the network chooses the LO timing offset based on reported MR wake-up delay and SSB periodicity so that enough SSBs exist between LO and PO for synchronization and measurements. LP-SS is therefore the mechanism that lets the LR bridge the timing and measurement gap without powering the MR [2507.10207].

Two receiver types are considered in the Release-19 paper. The first is the **Envelope/Energy Detector (ED)**, which is simpler and lower energy and can decode OOK-modulated LP-WUS. The second is the **Coherent Detector (CD)**, which can correlate among multiple ON-sequences and decode faster, but with higher power and complexity. The baseline low-power assumption is that the LR is built around the lower-complexity detection path and that the MR wakes only after LP-WUS indicates that paging should be decoded [2507.10207].

From an implementation perspective, LP-SS and LP-WUS are designed to fit into the standard gNB transmit chain. Both are generated in the time domain, transformed by DFT, and mapped onto the standard OFDM resource grid. This matters because LP-SS is not positioned as a detached auxiliary waveform; it is specified as a low-power-compatible reference integrated into the NR physical-layer framework and supported by the Release-19 specifications and change requests cited by the paper, including versions of **TS 38.211, TS 38.212, TS 38.213, TS 38.215**, and running CRs for **TS 38.331** and **TS 38.304** [2507.10207].

## 4. Packet-based LP-SS design patterns: the BLE multi-IMU case

A concrete non-cellular analogue of LP-SS appears in a **star-topology multi-IMU WSN** in which a **central DCU acts as synchronization master** and up to **8 IMU peripheral nodes** act as slaves. The design does not use a separate high-overhead synchronization protocol. Instead, the master sends **periodic low-cost BLE synchronization packets**, and the peripherals receive them in short, duty-cycled windows. Synchronization is tied to radio events rather than software interrupt latency through **MAC-layer timestamping via PPI** on both the master and the peripherals. The method is described as a **simplified FTSP-like scheme**: the master periodically sends sync packets in a BLE star network, but **without clock drift compensation** [2309.14867].

Several implementation choices make the design LP-SS-like in the strong sense of low-cost synchronization signaling. The paper explicitly prefers **advertising packets** over connection-based BLE events because advertising minimizes access time to the microsecond range, whereas connection-based access latency is very large and variable. On the master side, synchronization transmissions are inserted between ordinary BLE traffic by requesting radio timeslots through the **Nordic Timeslot API**. High-precision radio triggering and timestamp capture are handled through **PPI**. The synchronization timer is derived from the **32 MHz crystal**; two 16 MHz timers are combined, yielding **62.5 ns resolution**, a **1 ms wrap-around**, and a **49.71 day** overflow interval. The authors note that a lower-power **32.768 kHz crystal** would reduce power but would worsen timing to about **±30 μs per tick**, and they retain the higher-accuracy crystal because its incremental power cost is negligible relative to continuous BLE activity [2309.14867].

The timing error model is written as
\[
\tau = t_s + t_a + t_{tx} + t_p + t_r + t_{IMU},
\]
where \(t_s\) is send time, \(t_a\) access time, \(t_{tx}\) transmission time, \(t_p\) propagation time, \(t_r\) reception time, and \(t_{IMU}\) the IMU sampling time contribution. The discussion identifies the dominant adjustable terms as BLE **access time** and **receiver window length**; propagation is negligible, and send time is deterministic. On the master, the UTC time received from the tablet is passed via UART from the STM32 to the nRF52832, and **PPI captures timer values** at the beginning of an allocated timeslot. The CPU then copies the captured values into the transmitted packet. That CPU-copy stage is reported to take **29 μs** under the authors’ compiler settings, and the fixed delay can be compensated at the receiver. On the peripheral, PPI captures the local timers immediately when the correct BLE address is received, after which the interrupt handler computes and applies the synchronization offset so that each received sync packet re-aligns the local timer to the master’s [2309.14867].

The resulting power–precision tradeoff is explicit:

| Receive window length | Peripheral energy consumption |
|---|---:|
| 0 s | 74,844 mJ/h |
| 1 s | 12,016 mJ/h |
| 5 s | 2,401 mJ/h |
| 10 s | 1,202 mJ/h |
| 20 s | 597 mJ/h |
| 60 s | 198 mJ/h |
| 300 s | 40 mJ/h |

In the **highest-accuracy mode**, the master sends sync packets at **30 Hz**, the peripherals keep their receive window effectively continuous, and the measured synchronization error is **less than 1 μs**, with added peripheral energy consumption of **74.8 J/h**. In the **power-optimized mode**, reception is duty-cycled and enabled only until a sync packet is received; with a **1 minute interval** between receive windows, the synchronization error is about **±200 μs**, and energy consumption drops to **198 mJ/h**. This is sufficient because the application’s allowed packet-level synchronization error is **5 ms**. The IMU side is buffered through **oversampling at 225 Hz** while the user-level sampling rate is **100 Hz**, and the oversampling error is stated to have a maximum of **4.4 ms**, so even the relaxed radio-level synchronization point remains inside the application bound [2309.14867].

The paper is also notable for its explicit statement that the goal is not maximal precision but an **accurate enough** solution for synchronized IMU sampling. Measured raw IMU clocks justified that choice: two nominally identical IMUs operating at a nominal **100 Hz** were observed at **103.5 Hz and 104.4 Hz**, with a drift spread of **±2 Hz** over **30 minutes**. A plausible implication is that LP-SS design in constrained systems is often governed less by absolute synchronization extremity than by how precisely the synchronization layer must support the end application’s true temporal tolerance [2309.14867].

## 5. LPWAN, LoRa, and backscatter interpretations of LP-SS

Outside 3GPP, LP-SS is often not a formal channel name but a functional abstraction. The literature supports treating short, low-cost preambles or ambient timing anchors as LP-SS-like when they provide packet acquisition, coarse timing, and frequency-offset support under low-power or low-SNR constraints [2507.23029] [2502.08485] [2506.01743].

In one LPWAN design, the conventional DSSS preamble is replaced by a **CSS preamble** consisting of a **down-chirp** followed by an **up-chirp** that is its complex conjugate. The receiver performs **double-peak detection**: it correlates against the down-chirp, locates the first peak, then searches near the predicted location of the up-chirp peak. Because carrier frequency offset shifts the down- and up-chirp peaks in opposite directions, the same two chirps support **joint SOP detection and coarse CFO estimation**. The method also uses **CFAR** thresholding and a **peak-ratio validation rule**. The paper’s rationale is that chirps are more tolerant to CFO than DSSS preambles, that the shorter preamble reduces transmission energy overhead and processing latency, and that the synchronization function does not require a long training sequence in the targeted regime. Reported detection performance includes **\(P_D = 99\%\) at about \(-5\) dB under AWGN**, **\(P_D = 95\%\) at about \(5\) dB under Rayleigh fading**, and overall receiver sensitivity around **\(-122\) dBm** at the benchmark settings [2507.23029].

In LoRa, the preamble is the weak synchronization signal that must be exploited even when the spread signal lies **multiple orders of magnitude below the thermal noise floor**. The cited work argues that **sampling frequency offset (SFO)** cannot be treated as a late-stage impairment, because it distorts the preamble itself and thereby corrupts the usual CFO and STO estimators. Its proposed remedy is a **two-pass** procedure: estimate SFO early from the preamble, compensate it before the main CFO/STO estimators run, and then repeat the synchronization chain. For **SF \(12\)**, **\(\gamma=32\) ppm**, a **12.25-symbol preamble**, and **8 payload symbols**, compensating SFO in both the preamble and the payload yields a **6 dB SNR gain** at target SER \(10^{-3}\) relative to payload-only compensation, and the final performance is about **1 dB** from the ideal case with no SFO [2502.08485]. This suggests that in ultra-low-SNR LPWANs, the low-power synchronization signal is inseparable from impairment modeling; the synchronization waveform and the oscillator-error model must be co-designed.

Backscatter research offers another LP-SS interpretation. The survey explicitly notes that it does not define LP-SS as a separate formal acronym, but its content supports the idea of low-power synchronization signals as **ambient or specially exploited RF features/signals that let passive tags determine timing boundaries with minimal energy**. LTE-based systems such as **LScatter** and **SyncLTE** exploit **PSS/SSS/RS** as periodic ambient anchors; WiFi-based **SyncScatter** uses a two-stage wake-up frontend with passive activity detection followed by precision symbol tracking; and **PassiveBLE** performs symbol-level synchronization through **frequency difference detection** using **SAW filters** and beat-frequency extraction. Reported operating points include **150 ns timing accuracy** and **30 μW power** for SyncScatter, **9.9 μW ASIC** for PassiveBLE, and a **22.4×** synchronization-error reduction for SyncLTE relative to LScatter [2506.01743]. The survey’s broader conclusion is that the best low-power synchronization designs exploit existing structured signals, reduce synchronization to lightweight features such as envelope or correlation cues, and separate coarse wake-up from fine boundary alignment [2506.01743].

## 6. Fundamental limits, misconceptions, and open directions

The strongest theoretical caution against treating LP-SS as a negligible overhead comes from satellite wake-up via deterministic identification. That work introduces an explicit synchronization model based on a **phase-encoded coherent-state clock** in which the satellite emits a repeated sequence with time index represented by equidistant phase rotations on the unit circle. Identification codes improve with blocklength, but synchronization does not: the probability of remaining synchronized over the block decays exponentially, summarized by
\[
\tilde{P}_k \sim 2^{-k I(a,T)}.
\]
The paper states the asymmetry directly: **at any transmission power, identification performance improves with blocklength, whereas synchronization accuracy degrades** [2606.08845].

The quantitative consequence is severe in the reference scenario. For **\(d=1000\,\mathrm{km}\)**, the free-space transmittivity is reported as approximately **\(5.2 \times 10^{-16}\)**. With identification energy **\(E_{\mathrm{id}} = 3 \times 10^{-6}\)** photons per slot, synchronization parameters **\(q=0.995\)** and **\(\epsilon=0.25\)**, and target synchronization survival probability **\(\tilde P_k \ge 0.9999\)**, the identification-optimal blocklength is **\(k^\star \approx 5.04 \times 10^{6}\)**, but at that point **\(\tilde P_{k^\star}(E_{\mathrm{id}}) \approx 0\)**. To make synchronization reliable at the same blocklength, the minimum received clock energy is **\(E_{\mathrm{clock}}^\star \approx 1.66 \times 10^{2}\)** photons per slot, with corresponding transmitted clock energy **\(E_{\mathrm{tx,clock}}^\star \approx 3.17 \times 10^{17}\)**, producing an energy gap of about **\(5.5 \times 10^{7}\)** relative to identification energy [2606.08845]. The implication is not that LP-SS is intrinsically inefficient, but that synchronization cannot be abstracted away in extreme low-energy systems; a low-power wake-up or identification mechanism may remain infeasible unless the synchronization signal is included explicitly in the energy budget.

Several misconceptions therefore require correction. **LP-SS is not merely a smaller synchronization block**; in Release 19 it is a low-power receiver reference with distinct measurement and wake-up-radio roles [2507.10207]. **LP-SS is not automatically the dominant or negligible term across all platforms**; in BLE multi-IMU systems, a deliberately simplified packet-based scheme without drift compensation can still satisfy a **5 ms** application bound at **198 mJ/h**, whereas in the satellite identification model the synchronization signal can dominate energy by several orders of magnitude [2309.14867] [2606.08845]. **LP-SS is also not a uniform waveform class outside cellular systems**; in backscatter and LPWAN research, it may be realized as an ambient LTE anchor, a WiFi preamble cue, a BLE beat-frequency feature, or a conjugate chirp pair rather than a standardized channel [2506.01743] [2507.23029].

The open research agenda is correspondingly broad. Backscatter work emphasizes **multi-tag scalability**, **adaptive synchronization in dynamic channels**, **ultra-low-power hardware realization**, **cross-technology synchronization**, **security against spoofed or jammed sync pulses**, and **benchmarking and reproducibility** as unresolved issues [2506.01743]. The satellite literature adds the problem of **error-correcting capabilities of bosonic codes under jitter** and argues for **joint optimization of identification and synchronization** rather than identification-first design [2606.08845]. Taken together, these results suggest that LP-SS is best understood not as a single waveform invention but as a design principle: synchronization must be made commensurate with the receiver’s energy budget, impairment environment, and application-level timing tolerance.

Source: https://www.emergentmind.com/topics/low-power-synchronization-signal-lp-ss