---
title: IQM Garnet Quantum Processor
url: https://www.emergentmind.com/topics/iqm-garnet-quantum-processor
type: topic
---

# IQM Garnet Quantum Processor

The IQM Garnet Quantum Processor is a superconducting transmon-based quantum processing unit (QPU) developed by IQM Quantum Computers. With a 20-qubit "qubit crystal" architecture, the Garnet device integrates advanced hardware, firmware, and software approaches to enable high-fidelity gate operations, scalable qubit control, and multi-qubit entanglement suitable for near-term algorithmic benchmarks and quantum information experiments. The processor features a modular, tileable design focused on cryogenic integration, optimized coupler engineering, robust calibration infrastructure, and a complete control stack, with systematic characterization through multi-level performance benchmarks.

## 1. Hardware Architecture and Physical Implementation

The IQM Garnet QPU utilizes 20 flux-tunable transmon qubits arranged in a 45°-rotated square lattice, forming an effective 5×5 grid interleaved with flux-tunable transmon couplers. The lattice configuration yields 30 bidirectional edges, providing each qubit with approximately three nearest neighbors, facilitating gate routing while remaining conducive to surface-code operations [2408.12433, 2601.20871].

Physical qubit parameters are as follows:

- **Transmon qubit**: Josephson energy $E_J/h \approx 20$ GHz, charging energy $E_C/h \approx 200$ MHz, anharmonicity $\alpha \approx -200$ MHz.
- **Idle and on-state ZZ coupling**: Idle $<10$ kHz, activated $ZZ \approx 50$ MHz, adjusted via flux bias on tunable couplers.
- **Coherence times**: Median $T_1 = 40\,\mu$s ($10$–$90^\mathrm{th}$ percentile: $30$–$50\,\mu$s), median $T_2^* = 25\,\mu$s ($15$–$35\,\mu$s) [2408.12433]. In independent work, $T_1=37\,\mu$s, $T_2=9.6\,\mu$s (Ramsey) [2601.20871].
- **Qubit readout**: Individual $\lambda/4$ resonators ($f_\mathrm{RO}$: $5.2$–$6.2$ GHz), grouped into three frequency-multiplexed feedlines (7+7+6), each filtered via Purcell filters to minimize relaxation.
- **Integration**: 3D flip-chip packages route 76 control lines (drive, flux, readout) per QPU, with multi-layer magnetic shielding, terminated in a Bluefors XLD dilution refrigerator (base $T \sim 10$ mK) [2408.12433].

The logical-to-physical mapping and required SWAP operations respect this fixed connectivity through algorithms such as SABRE [2601.20871].

## 2. Native Gate Set and Pulse Control

The Garnet processor supports a high-fidelity native gate set, primarily comprising:

- **PRX$(\pi/2)$**: Single-qubit $\pi/2$ (or arbitrary) rotations about the $X$ axis, implemented by Gaussian-enveloped DRAG pulses (pulse durations $20$–$40$ ns, $99.9\%$ fidelity) [2601.20871, 2408.12433].
- **CZ gates**: Two-qubit entangling operations using flux-pulsed couplers or dynamically tuned cross-resonance interaction. Typical gate durations $20$–$40$ ns ($99.5$% median fidelity), realized via flux bias activating the avoided crossing for a controlled-phase [2408.12433].
- **Virtual-Z (frame) gates**: Implemented in software, enabling zero-duration $Z$ rotations for phase corrections and efficient compilation.

All higher-level unitaries (e.g., CNOT, arbitrary $R_Z$) are decomposed into sequences of PRX and CZ gates. Pulse-level control is synthesized and modulated by a Python-based pulse compiler, parameterizing amplitude, frequency, phase, and duration [2601.20871].

**Table 1: Native Gate Operations and Durations**

| Operation         | Gate Duration | Fidelity         |
|-------------------|--------------|------------------|
| Single-qubit (PRX)| 20–40 ns     | 99.9% (0.1% err) |
| Two-qubit (CZ)    | 20–40 ns     | 99.5% (0.5% err) |

Pulse electronics comprise arbitrary waveform generators (AWG), digital-to-analog converters (DAC), sideband IQ mixing, and room-temperature signal conditioning, with real-time sequencing and triggering performed on field-programmable gate arrays (FPGA) [2408.12433, 2601.20871].

## 3. Calibration, Error Characterization, and Decoherence Modeling

Device characterization utilizes extensive calibration routines and benchmarking protocols:

- **Process fidelity** is defined as
  $$
  F_\mathrm{proc} = \frac{|\mathrm{Tr}(U_\mathrm{target}^{\dagger} U_\mathrm{impl})|^2}{d^2}
  $$
  where $U_\mathrm{impl}$ is derived by simulating the pulse sequence under a Lindblad master equation with time-dependent Hamiltonian terms and calibrated noise rates [2601.20871].
- **Decoherence** is described by Lindblad operators:
  $$
  \frac{d\rho}{dt} = -i[H(t), \rho] + \sum_k \gamma_k (L_k\,\rho\,L_k^\dagger - \frac{1}{2}\{\!L_k^\dagger L_k, \rho\!\})
  $$
  with $L_1 = |0\rangle\langle1|$ (energy decay, $\gamma_1 = 1/T_1$), $L_2 = \sigma_z$ (pure dephasing, $\gamma_2 = 1/T_2^*$, $1/T_2^* \simeq 1/T_2 - 1/(2T_1)$) [2601.20871].

Reported gate error rates are $0.1\%$ for single-qubit and $0.6\%$ for native two-qubit gates, with crosstalk measured at median –70 dB (flux) and –48 dB (drive) [2408.12433, 2601.20871].

Multi-qubit entanglement is certified via preparation and measurement of Greenberger-Horne-Zeilinger (GHZ) states, with $n=20$ qubits, and fidelity evaluated both with and without readout-error mitigation (REM). Raw GHZ fidelity drops below $0.5$ for $n>12$, but with REM, $F_\mathrm{GHZ}(20)=0.62$, satisfying the threshold for genuine 20-qubit entanglement [2408.12433].

## 4. Compilation Stack and Circuit-Level Optimization

The compilation pipeline is closely integrated with hardware-specific constraints and pulse-level calibration. Mapping high-level circuits to hardware is performed by:

- **Routing (SABRE algorithm)**: Inserts SWAPs to ensure circuit compliance with nearest-neighbor connectivity [2601.20871].
- **Gate-level optimization passes**: Four main transformations are benchmarked:
  - **Gate cancellation**: Removes adjacent inverse gates (e.g., $XX^\dagger$), achieving $14\,024$ eliminated gates over $371$ circuit runs, improving $68\%$ of circuits.
  - **Commutation analysis**: Reorders commuting gates to expose further cancellation.
  - **Rotation merging**: Merges contiguous $R_z$ rotations on the same qubit, eliminating $6\,512$ gates ($29\%$ of circuits improved).
  - **Identity elimination**: Removes trivial single-qubit identities ($55$ gates, $9\%$ of circuits improved) [2601.20871].

Pulse-level simulations propagate these optimizations to the control sequence, allowing end-to-end fidelity analysis. Correlation analysis with circuit features shows that total pulse duration is the leading predictor of process fidelity (Pearson $r=-0.74$, $R^2=0.55$); input gate count and circuit depth are also predictive but less so.

## 5. Benchmarking, Experimental Validation, and Quantum Volume

Comprehensive benchmarking is undertaken through both simulation and hardware execution:

- **GHZ and QFT circuits:** Experimental runs on the IQM Resonance Garnet device demonstrate job success rates of $100\%$ over $8$ runs. Gate cancellation provides minimal further optimization for inherently minimal circuits (GHZ), but achieves $70\%$ reduction (from $30$ to $9$ gates) and $85.7\%$ depth reduction (from $21$ to $3$) for QFT$_4$ circuits. Fidelity improvement is circuit dependent: QFT absolute fidelity remains low ($\sim 0.1$) reflecting circuit complexity and cumulative decoherence, while GHZ$_{12}$ exhibits modest post-optimization gains ($0.256 \rightarrow 0.288$) [2601.20871].

- **Quantum Volume (QV) and System CLOPS:** System quantum volume is $QV = 2^5 = 32$ (heavy-output probability $> 2/3\pm2\sigma$). Virtual circuit layer operations per second (CLOPS) for $QV=32$ is $\sim 2600$ [2408.12433].

- **Entanglement Benchmarking:** Certified 20-qubit entanglement is observed with GHZ state fidelity (REM applied) exceeding $0.62$ [2408.12433].

**Table 2: Summary of Core Performance Metrics**

| Metric                | Value                       |
|-----------------------|----------------------------|
| Two-qubit gate fidelity | $99.5\%$ (median)         |
| Single-qubit error      | $0.09\%$ (median)         |
| Crosstalk (flux/drive)  | –70 dB/–48 dB             |
| $T_1$ (median)          | $40\,\mu$s                |
| $T_2^*$ (median)        | $25\,\mu$s                |
| Quantum volume          | $32$                      |
| GHZ(20) fidelity (REM)  | $0.62$                    |

## 6. Application Studies and NISQ Algorithm Benchmarks

The hardware platform has been used for hardware-in-the-loop VQE and quantum simulation studies, including investigations of quantum phase transitions in the transverse-field Ising model (TFIM) [2601.17515]. In these applications:

- A depth-2, physics-inspired VQE ansatz was deployed on up to four physical qubits, using a resource-efficient batched protocol to ensure temporal calibration consistency.
- Hardware results reproduced qualitative ground-state energy trends and finite-size crossover, with shot-noise-limited error bars. However, hardware energy mean absolute errors ($\sim2.0$) systematically exceed those from ideal VQE, indicating significant impact from decoherence and control errors.
- Magnetic order parameters and long-range correlations suffer broadening and suppression, consistent with finite-temperature (noise) smearing.
- No additional error mitigation (readout or zero-noise extrapolation) is employed. These findings emphasize the importance of error mitigation for extraction of correlation-sensitive observables and highlight the current boundaries of NISQ-era hardware for quantitative many-body simulation [2601.17515].

## 7. System Integration, Software Stack, and Scalability Roadmap

The full-stack design encompasses:

- **Cryogenics and packaging:** Bluefors XLD dilution refrigerator with cascaded RF attenuation, two-tier magnetic shielding, 3D QPU integration, and low-crosstalk control signal routing [2408.12433].
- **Control Electronics:** IQM Quantum Control System (QCS) with modular AWGs, direct digital synthesizers, FPGAs for sequencing, and PXIe-based resource expansion.
- **Software infrastructure:** High-level job submission (OpenQASM, Qiskit, Cirq) via Cortex REST API; pulse-level experimentation and calibration using Python-based EXA; station control through systemd-integrated services. Remote access is facilitated by IP-KVM, UPS, firewalling, and automated monitoring.
- **Scalability roadmap:** Modular design enables scale-up to 54 and 150 qubits, employing hierarchical calibration (tile and system-level), crosstalk mitigation, enhanced thermal management, and FPGA-based resource aggregation. Calibration and drift tracking are targeted by machine learning methods and hierarchical routines [2408.12433].

The consolidated technical benchmarks, from single- and two-qubit gate error characterization to system quantum volume and entanglement certification, render the IQM Garnet platform a representative state-of-the-art device for benchmarking the capabilities and practical limitations of superconducting quantum processors in the noisy intermediate-scale regime [2408.12433, 2601.20871, 2601.17515].

Source: https://www.emergentmind.com/topics/iqm-garnet-quantum-processor