---
title: III-V/Si Hybrid Phase Shifters
url: https://www.emergentmind.com/topics/iii-v-si-hybrid-phase-shifters
type: topic
---

# III-V/Si Hybrid Phase Shifters

III-V/Si hybrid phase shifters are photonic devices that heterogeneously integrate III-V compound semiconductors with silicon (Si) photonic circuits to enable highly efficient, scalable optical phase control. These platforms exploit the high electro-optic activity of III-V materials—particularly multiple quantum wells (MQWs), or band-structure–engineered novel functional oxides—while leveraging scalable Si photonic integration. The combination results in phase shifters with ultra-low operating voltage, minimal power consumption, high bandwidth, and, in some variants, non-volatile programmability. III-V/Si phase shifters are foundational for integrated optical phased arrays (OPAs), programmable photonic integrated circuits (PICs), and energy-efficient neuromorphic and switching applications.

## 1. Device Architectures and Functional Principles

Two leading classes of III-V/Si hybrid phase shifters have been demonstrated: (a) electro-optic shifters based on MQW structures under reverse bias driven by the quantum-confined Stark effect (QCSE) [1904.01104], and (b) non-volatile phase shifters utilizing resistive switching (memristive) HfO₂/Al₂O₃ or BTO-HZO oxide stacks sandwiched between III-V and Si electrodes [2307.00429, 2305.14271, 2210.06979].

**MQW QCSE Phase Shifters:**  
The device integrates a p-InP/p-InGaAs/MQW/n-InP stack onto a Si ridge waveguide via adhesive-free wafer bonding on SOI substrates. The phase shift is tuned by applying a reverse-bias across the III-V PN diode, which modifies the real part of the refractive index in the MQW region via QCSE. The device typically features an Si ridge (500 nm wide, 231 nm deep), a mesa width of 2 µm (scalable to 4 µm or denser), and a III-V/Si taper for adiabatic mode transfer with <1 dB taper loss. The optical mode, confined in Si, couples evanescently into the MQW with a confinement factor $\Gamma \sim 0.23$ for 600 nm wide Si [1904.01104].

**Memristor-Integrated Phase Shifters:**  
These devices are realized by embedding HfO₂/Al₂O₃ (memristive) oxide stacks between a III-V (e.g., n-GaAs or n-InP) membrane and a p-type Si core. The resistive state of the oxide stack is controlled via voltage pulses, which nucleate or rupture conductive oxygen-vacancy filaments. This non-volatile switch modulates the local carrier concentration and thus the optical index via plasma-dispersion and/or charge trapping effects, enabling "set-and-forget" tuning of phase in Mach-Zehnder Interferometers (MZIs) and rings [2307.00429, 2305.14271].

**Ferroelectric FET-Driven MOS Shifters:**  
Here, a III-V/Si hybrid MOS phase shifter is voltage-programmed by a ferroelectric FET (FeFET) operating in source-follower mode. Multistate memory is obtained by exploiting the FeFET's remanent polarization, which persists even when the power is removed, thus realizing non-volatile phase programming [2210.06979].

## 2. Key Performance Metrics

The following table summarizes representative performance metrics for each class of III-V/Si hybrid phase shifter, based on data from the cited works:

| Technology                | VπL (V·cm) | Max φ (π, length in µm) | Power (static/dyn.) | Bandwidth      | Non-volatility | RAM (dB) | Endurance    |
|---------------------------|------------|------------------------|---------------------|----------------|---------------|----------|--------------|
| MQW QCSE                   | 0.225      | 2 (5,000)              | < 3 nW / <8 µW      | >1.6 GHz       | No            | 0.15     | --           |
| HfO₂/Al₂O₃ Memristor      | --         | >π (350)               | <35 pA static       | 1.9 GHz / 4 Gbps| Yes           | --       | >24 h stabl. |
| HfO₂ Memristor [2305.14271]| --         | 0.09 (47)              | <1 nW (set/reset)   | 100 ns set     | Yes           | --       | >800 cycles  |
| FeFET-driven [2210.06979]  | 0.077      | 1.25 (1,500)           | ∼13–96 pW           | ms (proof)†    | Yes           | 0.31     | >10¹¹††      |

† Demonstrated with ms pulses; sub-ns switching reported in literature for HZO.  
†† Reported for standalone FeFET devices.

MQW QCSE phase shifters achieve the lowest Vπ (0.45 V for 2π phase, L=5 mm), lowest residual amplitude modulation (RAM ≃ 0.15 dB across 1550–1650 nm), and static leakage currents of 1–3 nA at –1 V (i.e., <3 nW) [1904.01104]. Non-volatile memristor phase shifters operate at true zero power in the programmed state, with demonstrated six-level (multi-bit) storage, sub-ns to 100 ns programming, and extinction ratios up to 31 dB [2307.00429, 2305.14271]. FeFET-driven variants achieve 1.25π non-volatile shifts (1.5 mm), switching energies ≤3.3 nJ, and proven CMOS-compatible operation [2210.06979].

## 3. Analytical Formulations and Physical Mechanisms

**Phase Modulation in MQW QCSE Shifters:**  
The phase shift for a section of length $L$ is governed by:
$$
\Delta \varphi = \frac{2\pi}{\lambda} \Gamma \Delta n(V) L
$$
with the voltage-length product for π phase shift, $V_\pi L \approx 0.225$ V·cm (for 600 nm Si width, $\Gamma\simeq0.23$). For $L=5$ mm, $V_\pi = 0.45$ V for π, $V_{2\pi} = 0.9$ V at 1550 nm.

The QCSE effect arises from the field-induced tilt of the quantum well bands, shifting excitonic transitions and thus altering the real part of refractive index. The reverse-bias regime ensures minimal absorption (RAM ~0.15 dB) and dark current (~nA).

**Memristor-Induced Non-Volatile Index Change:**  
The optical index change is tied to trapped charge or filament-mediated carrier density adjustments. For HfO₂/Al₂O₃ devices, the plasma-dispersion relation is:
$$
\Delta n(x, y) = -6.2 \times 10^{-22} \Delta N_e(x, y) - 6.0 \times 10^{-18} \left[\Delta N_h(x, y)\right]^{0.8}
$$
Programmed via set/reset voltages (e.g., $V_{set} \simeq -17$ V, $V_{reset}>+5$ V), the devices retain $>π$ phase shift at 350 µm length, with $\Delta n_g \approx 2.70 \times 10^{-3}$, supporting up to 4 Gbps [2307.00429].

**FeFET Control:**  
The FeFET-driven phase shifter exploits the remanent polarization of HfO₂-ZrO₂ (HZO) gate oxide, with the phase shift set by:
$$
V_o = V_g - V_{th}
$$
where $V_{th}$ is the programmable threshold set by FeFET polarization. This allows for multistate, non-volatile operation.

## 4. Integration in Photonic Systems: OPA and Circuit-Level Implications

**Optical Phased Arrays (OPAs):**  
The MQW QCSE phase shifter is implemented in a 32-channel OPA with a 1×32 star coupler, 4 µm array pitch, and 2 µm emitter pitch. Phase-controlled lateral and spectral steering provides a 2D field of view of $28^\circ_\theta \times 51^\circ_y$ over 200 nm tuning range, with SMSR = 16 dB [1904.01104]. After gradient-descent phase calibration, the main-lobe FWHM reaches 0.78° (y) and 0.02° (θ), with peak optical quality.

**Programmable Integrated Photonics:**  
Non-volatile phase shifters enable energy-neutral static programming for MZI, filter, and ring modulation—ideal for memory, post-fabrication trimming, and analog weight storage in photonic neural networks [2307.00429, 2305.14271]. Memristor-based cells provide sub-ns programming, multi-level retention, with demonstrated “set-and-forget” operation. FeFET crossbar architectures enable array-level drive scaling, reducing channel count from $N^2$ to $2N+1$ in $N\times N$ configurations with demonstrated crosstalk immunity during programming [2210.06979].

## 5. Fabrication Methods and Scalability Challenges

**MQW QCSE Devices:**  
Steps include (1) defining Si waveguides via DUV lithography and RIE, (2) oxide-activation and direct III-V die bonding (InP MQW epi) on patterned SOI, (3) III-V mesa and QW etch, (4) multilayer lift-off metalization, (5) planarization, via opening, and shallow-etch grating fabrication [1904.01104]. Denser pitches (<4 µm) are currently lithography-limited, with pathway to <1 µm available via next-generation steppers. Uniform III-V bonding and minimal thermal crosstalk are ensured by reverse-bias operation.

**Memristive and FeFET Shifters:**  
Fabrication involves ALD deposition of high-κ oxides (HfO₂/Al₂O₃ or HZO), direct wafer bonding of III-V layers to SOI, mesa and contact etching, metallization, and standard backend integration [2307.00429, 2305.14271, 2210.06979]. All steps are CMOS-compatible (<400°C), and architectures support co-integration of III-V phase shifters, memristors, and FeFETs on a monolithic SOI platform.

## 6. Performance Benchmarking Against Competing Technologies

State-of-the-art III-V/Si hybrid phase shifters outperform all-Si thermo-optic and carrier-based modulators in voltage-length product, RAM, and static power. For comparison:

- Si thermo-optic: $V_\pi L \gtrsim 20$ V·cm, bandwidth $\lesssim 100$ kHz, power $\gtrsim$ mW.
- Si PN carrier-based: $V_\pi L \sim 1$–3 V·cm, RAM $\sim1$–2 dB, bandwidth $\sim$tens GHz, $P\lesssim2$ μW.
- III-V/Si MQW: $V_\pi L = 0.225$ V·cm, RAM = 0.15 dB, bandwidth $>1$ GHz, $P<3$ nW [1904.01104].

Non-volatile memristor and FeFET-shifters achieve $E_{set} < 1$ pJ/bit, true zero holding power, and analog/multilevel programming at sub-ms speeds, with endurance above 800 cycles (memristor) or $>10^{11}$ (FeFET) and static insertion losses as low as 0.28 dB for 47 µm length [2305.14271, 2307.00429, 2210.06979].

## 7. Limitations, Applications, and Future Directions

Remaining challenges include further reducing memristor set/reset voltages, optimizing oxide thickness and overlap factor to shrink $L_\pi$, suppressing cycle-to-cycle variability, and scaling III-V/Si bonding to 200 mm wafers for ultra-dense OPAs and programmable arrays. Integration of on-chip III-V lasers and amplifiers, monolithic driver electronics, and crossbar architectures are critical steps toward full solid-state LiDAR, neuromorphic computing, and logic photonics engines [1904.01104, 2307.00429, 2210.06979].

III-V/Si hybrid phase shifters provide a demonstrated pathway to scalable, energy-efficient, and high-speed optical phase control in photonic integrated circuits, with applicability spanning beam steering, broadband switching, non-volatile photonic memory, in-memory computing, and analog optical neural network implementations.

Source: https://www.emergentmind.com/topics/iii-v-si-hybrid-phase-shifters