---
title: Gm-C Dynamic Amplifiers in Neuromorphic & Clocked Designs
url: https://www.emergentmind.com/topics/gm-c-dynamic-amplifier
type: topic
---

# Gm-C Dynamic Amplifiers in Neuromorphic & Clocked Designs

Searching arXiv for the cited papers to ground the article in the provided research.
Tool call: arxiv_search({"query":"id:1409.0171 OR \"OTA based 200 GΩ resistance on 700 μm2 in 180 nm CMOS for neuromorphic applications\"","max_results":5,"sort_by":"relevance"})
A **Gm-C dynamic amplifier** is a circuit in which a transconductance stage, characterized by \(G_m\) or \(g_m\), drives a capacitor so that voltage gain, temporal dynamics, or both are determined directly by the \(G_m/C\) ratio. In the cited literature, the term appears in two distinct but related senses. In neuromorphic continuous-time circuits, an operational transconductance amplifier (OTA) is placed in feedback around a capacitor to realize exponential rise and decay with time constant \(\tau = C/g_m\), so that extremely small transconductance values emulate very large resistances and long time constants [1409.0171]. In clocked data-converter-oriented circuits, a Gm-C dynamic amplifier is an open-loop dynamic stage that charges a capacitor only during an amplification phase, with differential gain approximately \(A = G_m T / C\), where \(T\) is the effective amplification interval [2508.14637]. Both interpretations are centered on the same principle: a current proportional to input voltage is integrated on capacitance, but they differ in whether operation is continuous-time or clocked, whether feedback is present, and whether the primary objective is long biological time constants or residue amplification.

## 1. Conceptual scope and governing relations

The continuous-time formulation uses an OTA as a conductance element. In a **gm-C configuration**, the OTA is used in feedback around a capacitor \(C\), producing exponential decay with

\[
\tau = \frac{C}{g_m}
\]

and an effective resistance

\[
R_{\text{eq}} \approx \frac{1}{g_m}.
\]

At \(g_m = 5~\text{pS}\), this corresponds to \(R_{\text{eq}} \approx 200~\text{G}\Omega\), and with \(C = 250\) fF the time constant is approximately \(50\) ms; for \(C \approx 1\) pF, \(\tau\) approaches \(200\) ms [1409.0171]. In this usage, the Gm-C dynamic amplifier is primarily a time-constant generator.

The clocked formulation defines gain in the time domain. The output is described as

\[
V_{\text{out, diff}} \approx \frac{G_m T}{C} \cdot V_{\text{in, diff}},
\]

so that

\[
A = \frac{G_m T}{C}.
\]

Here the amplifier is **open-loop Gm-C**, uses clocked switches to alternate between reset and amplification phases, and charges an output capacitor only during a defined time window \(T\) [2508.14637]. In this usage, the Gm-C dynamic amplifier is a dynamic gain element rather than a continuous-time decay cell.

A common misunderstanding is to treat all Gm-C dynamic amplifiers as continuous-time OTAs. The literature shows otherwise. One paper explicitly states that the clocked implementation is *not* a traditional continuous-time OTA and is closer to a switched-capacitor or time-interleaved residue amplifier used in pipelined SAR ADCs, whereas the neuromorphic implementation is explicitly asynchronous and continuous-time [2508.14637].

## 2. Continuous-time gm-C dynamic amplifiers for long time constants

In the neuromorphic realization, the design target is **ultra-low transconductance** so that moderate on-chip capacitances can produce long decays. The reported OTA achieves \(g_m \approx 5~\text{pS}\) in only **700 \(\mu\text{m}^2\)** in **180 nm CMOS**, giving an equivalent resistance near **200 G\(\Omega\)** [1409.0171]. This directly addresses the requirement that neuromorphic systems may need **>100** such time-constant circuits on a single chip.

The dynamic behavior follows a first-order differential equation,

\[
C \frac{dV_{\text{out}}}{dt} = -g_m (V_{\text{out}} - V_{\text{ref}}),
\]

with solution

\[
V_{\text{out}}(t) = V_{\text{ref}} + (V_{\text{out}}(0) - V_{\text{ref}})\, e^{-t/\tau},
\qquad
\tau = \frac{C}{g_m}.
\]

The paper reports measured exponential decay with \(C_{\text{OTA}} \approx 250\) fF and \(g_m \approx 5\) pS, yielding an extracted time constant of about \(50\) ms, consistent with \(\tau = C/g_m\) [1409.0171]. Rising and falling edges were fitted with exponentials, and the authors note that **nonlinearity has no significant influence on the decay waveform**.

The stated application domain explains why such a circuit is termed a dynamic amplifier despite modest linearity by conventional analog standards. The long time constants of **10–100+ ms** are essential for **membrane time constants**, **presynaptic adaptation**, **postsynaptic current (PSC) traces)**, **synaptic learning rules** such as spike-timing dependent plasticity, and **driving neuromorphic memristor arrays** [1409.0171]. In these contexts, exact THD is less important than reliable exponential wave shaping over biologically relevant time scales.

The same OTA can also be used without feedback as a voltage-to-current converter. In that mode it forms PSC-like waveforms, whereas in feedback around a capacitor it realizes an exponential state variable. This suggests that, in neuromorphic practice, the Gm-C dynamic amplifier is often a multifunctional kernel generator rather than a narrowly defined gain stage.

## 3. Clocked open-loop Gm-C dynamic amplifiers

The 2025 design uses the term in a more specific sampled-data sense. The amplifier is controlled by clock phases, is reset in one phase, and amplifies only during another. During the **amplification phase**, switches connect the differential pair currents to the output capacitor, while during the **reset phase** internal and output nodes are discharged or shorted so that residual charge is removed [2508.14637].

Its top-level architecture has two parts. The **main Gm-C stage** is implemented as a **composite differential pair**, formed by two asymmetric differential pairs, and drives a capacitor where the output voltage is developed. The **constant-gm bias circuit** defines a **temperature- and supply-insensitive transconductance** and mirrors this bias to the main-stage tails [2508.14637]. Because the topology is open-loop, the text states that feedback-stability issues typical of OTAs do not apply; instead, accuracy depends on **gm linearity** and **gm stability**.

The differential current generated by the main stage obeys

\[
C \cdot \frac{d V_{\text{out, diff}}}{dt} = \Delta I_D \approx G_m \cdot V_{\text{in, diff}},
\]

and for constant input over the amplification interval,

\[
V_{\text{out, diff}}(T) \approx \frac{G_m T}{C} V_{\text{in, diff}}.
\]

Thus the gain is determined jointly by device transconductance, capacitor value, and timing [2508.14637]. The paper further states that the output is sampled at the falling edge of \(\phi_2\), which places the circuit squarely in the class of clocked dynamic residue amplifiers rather than continuous-time filters.

This clocked meaning of Gm-C dynamic amplifier is particularly relevant when gain must be maintained over a narrowly specified differential input range. The cited implementation targets nearly constant gain over \(-40\) mV to \(40\) mV and combines gm shaping with constant-gm biasing to suppress both nonlinear gain roll-off and temperature or supply drift [2508.14637].

## 4. Core circuit techniques

Two distinct architectural strategies are documented in the cited works.

In the ultra-low-\(g_m\) neuromorphic OTA, the architecture combines three techniques: a **PMOS differential pair with current splitting**, **source degeneration (local negative feedback)**, and **series-parallel current mirrors for huge current down-scaling** [1409.0171]. The input pair M1/M2 has

\[
\left(\frac{W}{L}\right)_{\text{M1,M2}} = \frac{61}{20},
\]

and each branch feeds a current splitter that takes only a **\(1/61\)** fraction of the differential-pair drain current. Source degeneration is implemented by transistors M3 and M4 operating in the linear region. The mirror network then applies an additional scaling of either **\(1/900\)** or **\(1/300\)**. The total small-signal transconductance is given as

\[
g_{m,\text{total}} =
N_{\text{split}} \, N_{\text{CScale}} \,
\frac{g_{m1}}{1 + \frac{\beta_1}{4\beta_3}}.
\]

The design intent is explicit: keep the **gm-critical** devices in **strong inversion** with bias currents in the **1–10 \(\mu\)A** range, and confine **weak inversion** operation to the final scaling stage, where currents are already extremely small [1409.0171].

In the high-linearity clocked amplifier, the main technique is **gm shaping through two asymmetric differential pairs** [2508.14637]. A single asymmetric pair uses transistor ratios \(m\frac{W}{L}\) and \(n\frac{W}{L}\) with \(m \neq n\), which shifts the \(G_m\)-versus-input curve horizontally. Two mirrored asymmetric pairs are then summed so that one pair’s \(G_m\) peak shifts to positive \(\Delta V_{\text{in}}\) and the other to negative \(\Delta V_{\text{in}}\), yielding a composite transconductance that is nearly flat around zero input. The total transconductance is described as

\[
G_{m,\text{total}}(\Delta V_{\text{in}})
=
G_{m,A}(\Delta V_{\text{in}})
+
G_{m,B}(\Delta V_{\text{in}}).
\]

The bias path then uses a **constant-gm bias circuit** based on transistors M24, M25, and resistor R1. The paper states that the resulting transconductance depends only on transistor geometry ratios and \(R_1\), not on temperature or supply voltage to first order [2508.14637].

A useful contrast emerges between the two designs. One attains extremely small \(g_m\) through cascaded reduction mechanisms while preserving input swing and area efficiency; the other shapes \(G_m(\Delta V_{\text{in}})\) and stabilizes it against temperature and \(V_{DD}\) so that sampled gain remains linear and repeatable. This suggests that “Gm-C dynamic amplifier” identifies a principle of operation rather than a single canonical topology.

## 5. Performance, operating limits, and trade-offs

The two implementations prioritize different figures of merit.

For the neuromorphic OTA, key measured metrics include a nominal **\(5\) pS** transconductance at \(I_{\text{bias}} = 1~\mu\text{A}\) and \(N_{\text{CScale}} = 1/900\), a measured mean of **\(5.9\) pS** with **\(\sigma = 2.1\) pS** across **65 instances on 13 chips**, and a maximum observed value of about **10 pS** [1409.0171]. The reported linear range is approximately **1.2 V input swing at 20% linearity error (\(\alpha\) metric)**. Flicker noise dominates in the **1 Hz–1 kHz** band, with measured noise of **950 \(\mu\text{V}_{\text{RMS}}\)** and equivalent noise density **30 \(\mu\text{V}/\sqrt{\text{Hz}}\)**. The input-referred offset over the same 65 instances has mean **9.9 mV** and standard deviation **75 mV**. Power is described as being in the **few-\(\mu\)W range**, with the text giving both the expression \(P_{\text{diss}} = 3 I_{\text{bias}} V_{DD}\) and a cited value of **2.7 \(\mu\)W** at \(1~\mu\text{A}\) and \(1.8\) V, while also noting an arithmetic estimate of **5.4 \(\mu\)W** under the same nominal quantities [1409.0171]. The paper explicitly acknowledges this discrepancy.

For the clocked high-linearity design, the principal reported numbers are a nearly constant gain over **\(-40\) mV to \(40\) mV**, **THD = 70.5 dB** for the proposed amplifier, and **THD = 49.3 dB** for the traditional amplifier under the stated sinusoidal-input and FFT conditions [2508.14637]. Under \(\pm 10\%\) supply fluctuation, temperature sweep from **\(-40^\circ\text{C}\) to \(120^\circ\text{C}\)**, and **1 mV** differential input, the gain distribution has standard deviation **262m** and range **15.1 to 16.3**, whereas the traditional Gm-C dynamic amplifier has standard deviation **1.9** and range **13 to 19.5** [2508.14637].

The trade-offs are correspondingly different. The neuromorphic design explicitly sacrifices THD performance and accepts **20% nonlinearity** because waveform exactness is secondary to area, swing, and time constant density [1409.0171]. The clocked design accepts greater circuit complexity, including additional input devices, a constant-gm bias cell, and common-gate isolation devices, in exchange for flatter gain and reduced temperature and supply sensitivity [2508.14637].

## 6. Applications, comparison points, and design implications

The neuromorphic paper identifies three concrete application classes. First, the OTA-C cell generates exponential voltage traces for **synaptic learning rules**, including windows of the form

\[
\Delta w(\Delta t) \propto e^{-|\Delta t|/\tau}.
\]

Second, when used as a voltage-to-current converter, it generates PSCs of the form

\[
I_{\text{PSC}}(t) = I_0 e^{-t/\tau},
\]

which are integrated on the membrane capacitance. Third, the OTA-C output can directly drive **voltage-dependent memristors**, for which the reported **1.2 V** output swing is compatible with thresholds described in related work [1409.0171]. The chip context includes a **neuron and synapse matrix implementing a novel plasticity rule** and **test structures for CMOS-integrated memristors**.

The same paper also situates its OTA against other low-\(g_m\) circuits. It reports an area of **0.0007 mm\(^2\)**, described as **15× smaller** than the smallest listed competitor, while retaining a **5–50 pS** transconductance range, **30 \(\mu\text{V}/\sqrt{\text{Hz}}\)** noise density, and a comparatively large **1.2 V** swing [1409.0171]. The comparison is careful to note that other designs often use stricter linearity metrics such as **THD \(\le 1\)–5%** or \(\alpha = 5\%\), whereas this OTA uses **\(\alpha = 20\%\)**. The implication is not that the device is generically superior, but that it is specifically optimized for neuromorphic wave shaping.

The 2025 paper extracts a different set of design guidelines. It recommends gm shaping through two asymmetric pairs for linearity, a **constant-gm bias cell** for temperature and supply stability, explicit design through the relation \(A = G_m T / C\), reset switches to suppress memory and charge sharing, and **one-time post-fabrication calibration** through \(R_1\) or alternative bias trimming to handle process variation [2508.14637]. This suggests that, in sampled-data environments, the main concern shifts from ultra-low transconductance density to predictability of gain across input amplitude and PVT.

Taken together, the cited works present the Gm-C dynamic amplifier as a broad circuit class unified by capacitor integration of a transconductance-generated current, but differentiated by operating regime and optimization target. In one branch, the central objective is ultra-low \(g_m\), large effective resistance, and long exponential time constants in minimal silicon area [1409.0171]. In the other, the central objective is open-loop dynamic gain with high linearity and high temperature and power supply voltage stability through asymmetric-pair gm shaping and constant-gm biasing [2508.14637].

Source: https://www.emergentmind.com/topics/gm-c-dynamic-amplifier