---
title: 'FP8 Arithmetic: Formats, Methods & Acceleration'
url: https://www.emergentmind.com/topics/fp8-arithmetic
type: topic
---

# FP8 Arithmetic: Formats, Methods & Acceleration

A floating-point 8-bit (FP8) arithmetic system refers to a family of number representations and computation algorithms using 8-bit words to encode signed real values with a non-uniform (logarithmic) dynamic range. FP8 arithmetic has emerged as a critical enabler for high-throughput machine learning training and inference, and for accelerating double-precision matrix multiplication (DGEMM) via low-precision emulation schemes on modern hardware. The canonical FP8 formats, E4M3 and E5M2, are supported on NVIDIA Hopper/Blackwell, Intel Gaudi, and Open Compute Project (OCP) accelerator platforms. Use cases range from neural post-training quantization to numerically precise scientific computation via emulation, and span both digital and nontraditional substrates (such as iontronic and neuromorphic). The following provides a rigorous exposition of FP8 arithmetic’s formats, algorithms, hardware, numerical properties, and empirical impact.

## 1. FP8 Number Format Definition and Encodings

The standard FP8 word encodes a real number as a triplet: sign (s), exponent (e), and mantissa/fraction (m), parameterized by exponent width E and mantissa width M, with 1+E+M=8. The most widespread encodings are:

| Format   | Sign | Exponent (bits) | Mantissa (bits) | Bias | Min Normal     | Max Normal     | Epsilon  |
|----------|------|------------------|------------------|------|---------------|---------------|----------|
| E4M3     |   1  |        4         |        3         |   7  | $2^{-6}$      | $\sim$480      | $2^{-3}$ |
| E5M2     |   1  |        5         |        2         |  15  | $2^{-14}$     | $\sim$57,344   | $2^{-2}$ |

Normal values ($1 \leq e \leq 2^E-2$):

$$x = (-1)^s \times 2^{e-\text{bias}} \times (1 + m/2^M)$$

Subnormals ($e=0$, $m\neq0$):

$$x = (-1)^s \times 2^{1-\text{bias}} \times (m/2^M)$$

Special encodings follow IEEE-754 for E5M2 (full Inf/NaN support), while E4M3 omits Infs, repurposing the terminal exponent for an extra normal binade, enabling greater dynamic range at the expense of explicit infinity representation [2209.05433]. Subnormals permit gradual underflow and are critical for small magnitude representation [2310.13513].

The FP8 dynamic range, precision, and quantization grid depend on exponent/mantissa split; high E/low M favors range over granularity and vice versa.  E5M2 spans $\sim10^9$, ideal for dynamic gradients and Adam moments [2409.12517], while E4M3’s $\sim10^5$ range is suited for weights/activations [2208.09225].

## 2. Mathematical Operations and Rounding in FP8

Arithmetic on FP8 is realized by specialized or emulated fused multiply-add (FMA), addition, subtraction, and comparison operations. Implementations fall into three principal categories:

- **True digital floating-point arithmetic** using IEEE-style normalization, exponent alignment, mantissa (1+M)-bit adders/multipliers, sticky and guard bits, and rounding to nearest-even. The rounding operation heavily limits effective accuracy, with final quantization error proportional to the unit roundoff $\epsilon=2^{-M}$.
- **Integer-based emulation** for small mantissas, expressing FP8 arithmetic via integer adder/multiplier logic with conditional carry corrections for correctly rounded results under diverse rounding modes (round-to-nearest, toward zero, etc.) [2406.18441].
- **Spatial combinational and spiking approaches** leveraging native logic gates in unconventional substrates, with bit-exact pipelines upholding IEEE-754 rounding and normalization by propagation of sticky signals and leading-zero detectors [2512.07724].

Pseudocode for “classical” addition and multiplication:

Addition:
1. Unpack and align exponents (shift smaller’s mantissa).
2. Add/subtract mantissas with sign.
3. Renormalize (possibly two-bit shift), adjust exponent.
4. Round to nearest-even, clamp for over/underflow, repack.

Multiplication:
1. e_out = e_A + e_B – bias.
2. m_out = (1 + m_A/2^M) · (1 + m_B/2^M).
3. Normalize, round to nearest-even, saturate as needed, repack [2209.05433, 2310.13513].

## 3. Quantization, Dequantization, and Practical Deployment

FP8 is deployed primarily as a quantization target for full-precision data (commonly FP32 or BF16) in deep neural network weights, activations, and optimizer states [2312.05725, 2503.09975, 2505.20839]. The standard approach is affine mapping via a scale $s$:

- Quantization: $x_\text{fp8} = \mathrm{FP8\_round}(x/s)$ (to nearest-even, saturate/clamp at representable extrema).
- Dequantization: $\hat{x} = s x_\text{fp8}$ (restoring approximate dynamic range).

Scales are typically selected as
$$s = \frac{\max |x|}{\max(\mathrm{FP8})}$$
where the denominator is max normal (e.g., 240 for E4M3) [2510.24061, 2503.09975]. Per-tensor or per-channel scaling is routinely used to minimize clipping/underflow in high dynamic range tensors, with layer-wise (activation) and channel-wise (weight) granularity yielding the best empirical tradeoff for transformers and LLMs [2312.05725, 2503.09975].

FP8 quantization is especially robust to outliers due to its logarithmic level spacing, outperforming INT8 and bfloat16 on tasks with heavy-tailed tensor distributions (transformers, residual adds) [2208.09225, 2312.05725, 2505.20839]. Quantization-aware retraining is optional but narrows all performance gaps [2208.09225].

## 4. Algorithmic Acceleration: DGEMM Emulation via FP8 (Ozaki Schemes)

Emerging high-performance processors exhibit much higher throughput for INT8/FP8 matrix multiply-accumulate (MMA) than for FP64 [2603.10634, 2508.00441]. Emulating double-precision (FP64) GEMM (DGEMM) is now possible and highly efficient with FP8 tensor cores using the Ozaki-I and Ozaki-II schemes:

- **Ozaki-II approach (optimal for FP8)**: FP64 A, B are scaled to large integers, decomposed into residue classes modulo coprime $p_\ell$, split into FP8 fragments (via Karatsuba or modular reduction), MMA is performed entirely in low precision (FP8-in, FP32-accumulate, exact for practical $k\leq2^{16}$), and results are recombined using Chinese Remainder Theorem, followed by inverse scaling. Guaranteed elementwise error is $\lesssim 2^{-53}|AB|$.
- For DGEMM via the Ozaki-II scheme, the number of required FP8 matrix multiplications is a strict multiple (e.g., 37 for N=12 moduli) less than in the best Ozaki-I mapping (121 for S=11 slices), with identical effective bit accuracy [2603.10634].

Benchmarks show FP8 Ozaki-II emulation achieves $61\,\mathrm{TFLOP/s}$ on NVIDIA B200 (FP8 MMA throughput $4.5\,\mathrm{PFLOP/s}$), and that when FP8 hardware throughput is more than twice that of INT8, FP8-based Ozaki-II is optimal [2603.10634].

## 5. Hardware Implementations and Acceleration Pathways

FP8 arithmetic is natively implemented in multiple hardware architectures:

- **NVIDIA H100, Blackwell, and Rubin tensor cores**: E4M3/E5M2 formats with full IEEE or slightly modified handling, fused multiply-add engines accepting FP8 input, accumulating in FP16/FP32, and saturating or trapping on overflow.
- **Intel Gaudi 2**: AVX10.2-compliant OFP8 E4M3/E5M2 pipeline supporting per-tensor/per-channel scale, high-precision accumulation, optimized power-of-two scaling fused into exponent adders for in-core efficiency [2503.09975].
- **FPGA and ASIC**: Integer operations implement correctly rounded FP8 arithmetic with LUT-based carry-in logic, yielding $2\times$ faster, $>2\times$ smaller resource multipliers compared to bit-serial designs; E4M3 requires more complex rounding logic than E5M2 but still fits in a per-stage LUT [2406.18441].
- **Experimental spatial neuromorphic platforms**: Bit-exact E4M3 arithmetic is achievable through spatial combinational pipelines of integrate-and-fire neurons, with explicit sticky/guard bit propagation, yielding $17\times$ latency reduction for large linear layers relative to temporally coded SNNs, and full robustness to analog noise and leakage [2512.07724].

Synthesis and validation efforts confirm full alignment with PyTorch/numerical reference for all 16,129 E4M3 value pairs (normal/subnormal/NaN/Inf) [2512.07724].

## 6. Numerical Behavior, Empirical Performance, and Limitations

FP8 enables significant memory footprint reduction (2–4×), bandwidth scaling, and energy savings per operation ($\sim0.1\,\mathrm{pJ}$ for 8-bit FMA vs $\sim0.2\,\mathrm{pJ}$ for FP16) [2504.21197]. Empirical studies demonstrate:

- End-to-end FP8 quantization (E4M3/E5M2) matches FP16/BF16 baselines for vision, language, and LLM tasks, typically within $<0.3\%$ accuracy drop (e.g., BERT on GLUE: 84.6% FP32 vs. 84.6% FP8; ResNet-50 on ImageNet: 76.13% FP32 vs. 75.85% FP8) [2312.05725, 2104.07329, 2209.05433].
- For FFT-based spectral computations, both E4M3 and E5M2 are unsuitable due to catastrophic overflow in all but extremely low-dynamic-range cases, providing a clear warning of FP8’s limitations outside deep learning [2504.21197].
- In LLM fine-tuning and LoRA adapters, FP8 only improves net speed when quantization overhead is amortized (i.e., large GEMMs). For small matrices, quantization setup costs dominate [2510.24061].
- In long-horizon FP8 training (trillion tokens), FP8-specific instabilities are observed in SwiGLU activations, rectified via “Smooth SwiGLU” per-channel scaling. Both moments of Adam can be safely quantized (E4M3/E5M2 respectively) only if appropriate dynamic range is preserved [2409.12517].

## 7. Format Parameterization, Flexible Schemes, and Best Practices

FP8 arithmetic enables a spectrum of format choices, trading range for precision, or vice versa, as a function of application layer, distribution tails, and resource constraints [2310.13513, 2104.07329, 2208.09225]:

- Intense dynamic range requirements (gradients, Adam v): E5M2 or even narrower mantissa/broader exponent (E2M5, 2M5E).
- Most activations, weights: E4M3, E3M4.
- Strictly nonnegative ReLU activations: assign the sign bit to exponent/mantissa for even higher density.
- Flexible (FFP8) formats permit layerwise (or tensorwise) optimizations of exponent and mantissa allocation, exponent bias, and sign presence for $<0.4\%$ top-1 image classification loss without retraining, with only two lightweight bit converters at memory/computation boundaries [2104.07329].

Best practices include always using per-tensor or per-channel affine scalings, nearest-even rounding, maintaining high-precision accumulation in MACs, and benchmarking format tradeoffs on calibration data. For safety, non-GEMM (e.g., LayerNorm, GELU) ops are best kept in FP16/BF16 [2312.05725, 2209.05433].

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FP8 arithmetic has thus catalyzed a new design space for both AI and scientific hardware, facilitating deep compression, throughput scaling, and algorithm/hardware co-design. Its main limitations remain restricted precision for scientific reduction (without emulation), and catastrophic overflow for high-dynamic-range non-learned signals. Within coverage and with careful quantization, FP8 now stands as the default low-precision arithmetic for inference/training acceleration in large language and vision models, and is the enabling substrate for high-throughput FP64 emulation in emergent GPU and NPU architectures [2603.10634, 2312.05725, 2503.09975, 2510.24061, 2104.07329, 2406.18441, 2512.07724].

Source: https://www.emergentmind.com/topics/fp8-arithmetic