---
title: FeFET-based QUBO Solvers for Combinatorial Optimization
url: https://www.emergentmind.com/topics/fefet-based-qubo-solvers
type: topic
---

# FeFET-based QUBO Solvers for Combinatorial Optimization

FeFET-based QUBO solvers are specialized hardware accelerators leveraging ferroelectric field-effect transistors (FeFETs) within compute-in-memory (CiM) or oscillator-based architectures to solve quadratic unconstrained binary optimization (QUBO) problems. These solvers exploit the non-volatility, analog programmability, and high endurance of FeFET devices for both encoding problem coefficients and in-memory computation, providing an energy-efficient, fast, and scalable alternative for tackling combinatorial optimization problems (COPs) with or without constraints. Several architectures, including the HyCiM system and FeFET-coupled oscillator Ising machines, have demonstrated substantial improvements in search-space reduction, area efficiency, and computation speed, with practical performance validated on non-trivial problem instances such as quadratic knapsack, graph coloring, Max-Cut, and MIMO detection [2410.14111][2309.13853][2511.00479].

## 1. QUBO Formulation and Mapping to FeFET Hardware

QUBO problems are expressed as
$$
E(\mathbf{x}) = \mathbf{x}^T Q\,\mathbf{x}
$$
with binary variables $\mathbf{x} \in \{0,1\}^n$ and coefficient matrix $Q \in \mathbb{R}^{n \times n}$. The binary optimization can encode COPs, including those represented by Ising Hamiltonians via the mapping $\sigma_i = 1-2x_i$:
$$
H_P(\boldsymbol{\sigma}) = \sum_{i<j} J_{ij} \sigma_i \sigma_j + \sum_i h_i \sigma_i
$$
with $E(\mathbf{x}) = \mathbf{x}^T Q \mathbf{x}$ after transformation [2309.13853][2410.14111].

FeFET-based solvers map this QUBO directly onto crossbar arrays, exploiting the programmable multilevel $V_{\text{th}}$ of FeFETs to represent matrix coefficients with digital or analog precision. For problems with constraints—especially inequality constraints (e.g., knapsack-type)—conventional D-QUBO approaches penalize violations within the objective, necessitating large numbers of auxiliary variables and significantly expanding the state space ($2^{n+C}$ for $n$ variables and constraint $C$). FeFET architectures such as HyCiM instead separate feasibility checking and energy evaluation, allowing direct mapping of feasible configurations only [2410.14111].

## 2. FeFET Device Architecture and Crossbar Implementation

FeFETs are three-terminal, CMOS-compatible transistors with a ferroelectric HfO₂ gate dielectric, providing high ON/OFF ratios (>10³), multilevel storage via polarization programming, endurance (>10¹⁰ cycles), and ≥10-year data retention. In a 28 nm process, FeFETs can be structured as 1FeFET–1R cells to further suppress read variation [2309.13853][2511.00479].

Crossbar arrays organize FeFET cells to implement parallel vector-matrix-vector (VMV) multiplication ($E(\mathbf{x}) = \mathbf{x}^T Q \mathbf{x}$) in a single computational step:

- **Data Encoding:** Input variables $x_i$ are supplied on wordlines (WL), and coefficients $Q_{ij}$ are represented by programmable $V_{\text{th}}$ in FeFETs or by conductance in crossbar patterns.
- **Parallel Computation:** For each SA iteration, candidate $\mathbf{x}$ is broadcast, row and column currents representing energy are summed and digitized; at M-bit precision, multiple bit-sliced crossbars or per-cell quantization can be employed.
- **Scalability:** Arrays are implemented at 32×32 size in silicon with tiling to support $\sim 1000$ variables; lossless matrix compression further improves density [2309.13853].

## 3. FeFET-based Solvers for Constrained QUBO: The Inequality-Filter Paradigm

Traditional D-QUBO methods for combinatorial problems with constraints require embedding
$$
\sum_{i=1}^n w_i x_i \leq C
$$
as a penalty, leading to an augmented space ($2^{n+C}$). The HyCiM architecture introduces a novel transformation that enforces constraints via a dedicated inequality-checking circuit (the "inequality filter") prior to QUBO energy evaluation [2410.14111]:

- **Device-circuit co-design:** Each inequality-filter cell is a 1FeFET–1R stack, storing multi-level weights and supporting current-mode, phase-based comparison of partial sums.
- **Array operation:** An $m \times n$ array stores weights across $n$ columns, with match-line voltages encoding $\sum w_i x_i$. A replica array encodes the constraint $C$; a two-stage comparator passes only feasible $\mathbf{x}$ for VMV evaluation.
- **Impact:** This approach removes the need for auxiliary bits, reducing the search space from up to $2^{2536}$ ($n=100$, $C \approx 2536$) to only $2^{100}$, and delivering hardware area savings of 88–99.96%.

## 4. Annealing Algorithms, Compression, and Computational Workflow

FeFET-based QUBO solvers commonly employ simulated annealing (SA) or enhanced variants such as MESA (multi-epoch SA):

- **Annealing Process:** At each iteration, candidate configurations $\mathbf{x}_{\rm new}$ are tested against feasibility constraints (if present), and energies $E_{\rm new}$ are computed in-place in the crossbar. Acceptance follows the Metropolis rule:
  $$
  P_{\rm accept} =
  \begin{cases}
    1, & \Delta E \leq 0 \\
    \exp(-\Delta E/T(t)), & \Delta E > 0
  \end{cases}
  $$
  with exponential or linear temperature decay [2410.14111].
- **Sparse QUBO Compression:** For sparse problems, compression maps the Q matrix to reduced-dimension blocks without energy loss; for example, producing dimension $p\times q$ with $p,q \ll N$, reducing area by 60–80% [2309.13853].
- **Oscillator Ising Machines:** Alternative architectures map QUBO couplings onto FeFET-controlled conductances in coupled oscillator arrays ("OIMs"). Oscillator phase synchronization, modeled by discrete Kuramoto dynamics, enables all-to-all QUBO minimization with time-to-solution scaling as $O(\log N)$ [2511.00479].

## 5. Performance Metrics and Experimental Results

FeFET-based QUBO solvers exhibit significant improvements in benchmarked metrics:

| Metric                | HyCiM (FeFET CiM)         | D-QUBO Baseline         | OIM (FeFET+CMOS)         |
|-----------------------|---------------------------|------------------------|--------------------------|
| Search Space          | $2^{100}$ (w/ filter)     | up to $2^{2636}$       | $2^{M}$ (M spins)        |
| Area Savings          | 88–99.96% vs. D-QUBO      | —                      | N/A                      |
| SA Time-to-solution   | $\sim 1$–$10\,\mu$s @ $n=100$ | $>100\times$ higher     | $O(\log N)$ scaling      |
| Solution Quality      | 98.54% success (QKP)      | 10.75% (QKP)           | Near-ML BER, $M\leq 100$ |

Additional results include:
- Energy per QUBO evaluation: $\sim$2 pJ (crossbar), 0.5 pJ (filter) [2410.14111].
- MESA achieves target energies in 10–100× fewer iterations than conventional SA [2309.13853].
- Ring-Oscillator FeFET OIMs achieve logarithmic computation time scaling for dense QUBOs such as MIMO detection, limited by conductance tuning windows (1–60 μS per device) [2511.00479].

## 6. Device- and System-Level Considerations

FeFET-based designs are subject to various device-level effects and practical system constraints:

- **Threshold Variation:** Device-to-device $V_{\rm th}$ variation $\sim 100$ mV; can be mitigated via calibration [2410.14111].
- **Conductance Tuning:** OIM performance is optimal for $G_{\min} \sim 1~\mu$S, $G_{\max} \sim 60~\mu$S; outside this window, coupling weakens or stalls.
- **Endurance and Retention:** HfO₂ FeFETs documented to $>10^{10}$ write/erase cycles and $>10$ years retention [2410.14111].
- **Scalability:** Demonstrated filter/annealer arrays range from 16×100 up to 256×256; crossbar chaining and compression allow scaling to $N\sim 1000$–$4096$ [2309.13853].
- **Noise and Robustness:** Simulated annealing and Kuramoto OIMs robust against analog noise; periodic refreshing mitigates drift.

## 7. Outlook and Application Domains

FeFET-based QUBO solvers offer a scalable platform for hardware acceleration of binary combinatorial optimizations:

- **Versatility:** Efficient support for both constraint-free and constrained COPs (e.g., quadratic knapsack, Max-Cut, graph coloring, ML MIMO detection).
- **Integration:** Three-terminal FeFETs compatible with advanced CMOS, enabling in-memory or near-memory compute paradigms.
- **Future Prospects:** Anticipated advances include denser 3D FeFET×CMOS integration, automated annealing protocols, expanded conductance range, and improved device uniformity. Applications extend to edge-AI, logistics, communication systems, and real-time optimization [2511.00479][2410.14111][2309.13853].

FeFET-based QUBO solvers thus represent a leading architecture in the evolution of hardware-accelerated combinatorial optimization, providing order-of-magnitude benefits in energy, area, and solution speed, while maintaining competitive or superior solution quality on established benchmarks.

Source: https://www.emergentmind.com/topics/fefet-based-qubo-solvers