--- title: Dynamic Threshold MOSFET (DTMOS) Scheme url: https://www.emergentmind.com/topics/dynamic-threshold-mosfet-dtmos-scheme type: topic --- # Dynamic Threshold MOSFET (DTMOS) Scheme A Dynamic Threshold MOSFET (DTMOS) is a metal-oxide-semiconductor field-effect transistor structure in which the device’s body (substrate) connection is dynamically altered to track the gate terminal. This results in a threshold voltage that varies in real time according to the gate voltage, yielding reduced leakage in the OFF-state and enhanced drive in the ON-state. The DTMOS architecture enables ultra-low power and high current efficiency, especially attractive for sub-threshold, near-threshold circuits and advanced analog front-ends. Extensions such as the Variable Threshold MOSFET (VTMOS), as well as analytical models for dynamic threshold control in SOI and double-gate devices, further expand its applicability in both digital and analog CMOS design [1003.6030][2601.01232][1211.4564]. ## 1. Principle of Dynamic Threshold Operation Conventional MOSFET threshold voltage ($V_{\mathrm{TH}}$) is governed by the body effect, typically expressed as: $$ V_{\mathrm{TH}}(V_{SB}) = V_{\mathrm{TH0}} + \gamma \left[ \sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F} \right] $$ where $V_{SB}$ is the source-to-body bias, $V_{\mathrm{TH0}}$ the zero-bias threshold, $\gamma$ the body-effect coefficient, and $\phi_F$ the Fermi potential. In DTMOS, the gate and body are directly tied together. For NMOS, $V_{SB} = V_{GS}$, so $V_{\mathrm{TH}}$ dynamically falls as $V_{GS}$ increases during ON-state, decreasing the channel barrier for conduction. Conversely, when OFF ($V_G = 0$), the threshold is maximized, resulting in minimum leakage. This toggling of $V_{\mathrm{TH}}$ enhances ON-current ($I_{ON}$) for strong switching and suppresses OFF-current ($I_{OFF}$) for leakage control, critical for circuits operating at $V_{DD}$ below $V_{\mathrm{TH0}}$ [1003.6030][2601.01232]. ## 2. Mathematical Models for DTMOS and Variants Dynamic threshold modulation is described quantitatively by: - **Body-effect:** $V_{\mathrm{TH}} = V_{\mathrm{TH0}} + \gamma \left[\sqrt{2\phi_F+V_{SB}} - \sqrt{2\phi_F}\right]$ - **DTMOS case:** $V_{SB} = V_{GS}$, so $V_{\mathrm{TH}}(V_{GS})$ decreases with increasing $V_{GS}$ - **Linearized approximation:** $\Delta V_{\mathrm{TH}} \approx -\eta V_{GB}$, with empirical $\eta$ In advanced double-gate or SOI FETs, full 2-D electrostatic models are employed, as in the Flexible-FET, where the top-gate threshold voltage $V_{\mathrm{th}}$ is analytically derived as a function of the bottom-gate voltage $V_{BG}$ via solution to the 2D Poisson equation using Young’s approximation. This yields explicit relations: $$ V_{\mathrm{th}}(V_{BG}) = \text{[complex functional relation; see eq. (17) in 1211.4564]} $$ This allows continuous threshold tuning from high to low, with the analytical solution benchmarking well with experimental and SILVACO-Atlas simulation data [1211.4564]. ## 3. Circuit Implementations: DTMOS and VTMOS Schemes **DTMOS circuits** adopt a direct gate–body connection (NMOS body = gate; PMOS body = gate). DTMOS inverters, NAND, and NOR gates follow standard CMOS topologies but substitute the body-gate tie for static body bias. **VTMOS** extends DTMOS by introducing a fixed DC offset ($V_{AN}$ for NMOS, $V_{AP}$ for PMOS) between gate and substrate: - NMOS: $body = gate - V_{AN}$, $V_{AN} \in [0, 0.2$ V$]$ - PMOS: $body = gate - V_{AP}$, $V_{AP} \in [0, -0.2$ V$]$ This enhances static power saving by further reducing both $I_{ON}$ and $I_{OFF}$ beyond pure DTMOS, with only incremental increase in propagation delay [1003.6030]. **Amplifier Applications:** In advanced analog designs, DTMOS is utilized to boost effective transconductance ($g_{m,\mathrm{eff}} = g_m + g_{mb}$), where the body transconductance ($g_{mb}$) increases small-signal gain and reduces input-referred noise without additional current or increased device size. This has been demonstrated in gain-boosted flipped-voltage-follower (FVF) front ends for bioimpedance sensing [2601.01232]. ## 4. Performance Analysis and Simulation Results ### Digital Logic (VTMOS/DTMOS vs CMOS) [1003.6030] | Architecture | Power Dissipation ($W$) | Propagation Delay (ns) | Power-Delay Product (PDP) | Supply Voltage (V) | |:---------------|:------------------------|:----------------------|:--------------------------|:-------------------------| | CMOS | $3.6 \times 10^{-10}$ | $22$ | — | $0.2$ (subthreshold) | | DTMOS (VAN=0) | Slightly > CMOS | $18$ | Reduced | $0.2$ | | VTMOS (0.2 V) | $1.6 \times 10^{-10}$ | $22$ | Reduced by $\sim$50% | $0.2$ | - **Power reduction:** VTMOS achieves up to $54\%$ lower static power vs CMOS. - **Delay trade-off:** Slight penalty in propagation delay with increased body offset. - **Frequency dependence:** Advantage persists up to ~8 MHz; at higher frequencies, dynamic power dominates. ### Analog Amplifier Front-Ends [2601.01232] | Configuration | Input Noise (nV/$\sqrt{\rm Hz}$) | Power ($\mu$W) | Bandwidth (MHz) | Closed Loop Gain (dB) | |:-------------------|:-----------------------------|:--------------|:---------------|:----------------------| | Baseline | 36.6 | 2.5 | 1.44 | 34 | | DTMOS-enabled FVF | 32.4 | 2.5 | 1.44 | 34 | | DTMOS + SDCM | 29.8 | 2.5 | 1.44 | 34 | - **Noise performance:** $11.6\%$ reduction in input-referred noise using DTMOS, up to $18.7\%$ with added source degeneration, with no increase in static current draw. - **Input impedance:** Drops from $\sim11\,$M$\Omega$ to $7\,$M$\Omega$ at $50$ kHz due to bulk-gate tie. - **Design constraints:** Signal swing and body-diode forward bias must be controlled to avoid forward conduction. ## 5. Physical Implementation and Device Modeling The DTMOS effect is achievable in single-gate bulk devices but is particularly compelling in SOI and double-gate structures. In Flexible-FETs, a bottom gate (JFET) modulates the potential profile in a fully-depleted channel. The top-gate threshold is controlled by the bottom gate via the solved 2D Poisson equation. Practical models derived and validated against experiment capture: - **Effect of channel doping ($N_D$):** Higher $N_D$ increases $V_{\mathrm{th}}$ and reduces tunable range. - **Si film and oxide thickness ($t_{si}, t_{ox}$):** Thicker channels or oxides increase $V_{\mathrm{th}}$ and weaken threshold control. - **Agreement with data:** Analytical models yield threshold predictions with $<50$ mV RMS error versus experimental and TCAD simulation results [1211.4564]. ## 6. Trade-Offs, Advantages, and Practical Considerations ### Advantages - **Ultra-low power operation:** Enables logic and analog circuits at $V_{DD}