---
title: Dynamic Circuit Qubit Reuse
url: https://www.emergentmind.com/topics/dynamic-circuit-based-qubit-reuse
type: topic
---

# Dynamic Circuit Qubit Reuse

Dynamic circuit-based qubit reuse is the compilation and execution paradigm in which a quantum circuit uses mid-circuit measurement, reset or reinitialization, and classical feedforward so that a single physical qubit can serve multiple logical roles over time. In a static circuit, the compiled width equals the number of logical qubits used; in a dynamic circuit, the compiled width can be strictly less than the original width because measured qubits are reset and rebound to later logical wires. Across the recent literature, the topic spans formal graph models of reuse, exact and heuristic compilers, modular-architecture mapping, error-aware scheduling, and specialized applications ranging from QAOA and QFT to modular QPU execution and Floquet codes [2210.08039] [2410.08817] [2506.09323].

## 1. Operational semantics and reuse conditions

A dynamic circuit is any quantum circuit that includes mid-circuit measurements and/or resets, enabling real-time classical feedforward and control during execution. Qubit reuse is the technique of measuring a qubit mid-circuit, resetting it to a known basis state, typically $|0\rangle$, and reusing it later in the same circuit to reduce physical qubit count or to recycle ancillas. The basic pattern is consistent across superconducting, trapped-ion, modular, and photonic settings: once a logical qubit’s final operation is completed and its state will not be needed except through its measurement outcome, the qubit can be measured and then reset to $|0\rangle$; subsequent operations may then be conditioned on the stored classical result rather than on a still-live quantum degree of freedom [2504.16579] [2506.09323] [2210.08039].

The central correctness requirement is that reuse must respect causal structure. In lifetime-based formulations, each logical qubit $q$ has an interval $[first\_idx(q), last\_idx(q)]$, and reuse is legal when intervals are disjoint, for example when $last\_idx(q_1) < first\_idx(q_2)$. In DAG-based formulations, reuse is valid only if the terminal of one logical wire can be connected to the root of another without introducing cycles or violating no-cloning constraints. The literature expresses this in several equivalent ways: there should not be any gate between reused logical qubits; no path from the earlier wire’s root to the later wire’s terminal may create a forbidden dependency; and a qubit is reusable only if it has no future entangling operations and any remaining effect is representable through a measurement outcome [2506.09323] [2410.08817] [2211.01925].

This makes dynamic reuse distinct from both static compilation and ordinary ancilla recycling. Static mapping maintains a one-to-one logical-to-physical correspondence throughout execution. Traditional ancilla management often treats recycling as a local within-core resource problem. Dynamic circuit-based reuse instead treats measurement, reset, and classical control as first-class compilation primitives, so that logical lifetimes can be shortened, peak concurrency reduced, and subsequent placement or routing decisions simplified [2506.09323] [2211.01925].

## 2. Formal abstractions and optimization objectives

A large part of the theory is built on graph representations. One family of models uses a circuit DAG whose vertices are roots, terminals, and gate nodes, with edges encoding causal flow. GidNET simplifies this to a biadjacency graph $G' = (R, T, E)$, where $R$ is the set of root vertices, $T$ is the set of terminal vertices, and $(r,t)\in E$ iff there exists a directed path $r \to t$ in the original DAG. The corresponding biadjacency matrix $B$ yields the candidate matrix
$$
C = 1_{n\times n} - B^\top,
$$
where $C[q^i,q_j]=1$ indicates a potential reuse edge from the terminal of $q_i$ to the root of $q_j$. Width reduction is then measured by
$$
r = \frac{W_{orig} - W_{comp}}{W_{orig}}.
$$
This candidate-matrix view makes reuse a graph-selection problem over causally permissible terminal-to-root links [2410.08817].

A second family of models expresses reuse as an exact acyclic edge-addition problem. In the binary integer programming framework for dynamic quantum circuit compilation, the simplified DAG is encoded by a biadjacency matrix $B$, the candidate reuse matrix is $\bar{B} = \neg(B^\top)$, and a binary matrix $F$ denotes added terminal-to-root edges. The modified adjacency matrix is
$$
A(G') =
\begin{pmatrix}
O_n & B \\
F   & O_n
\end{pmatrix},
$$
with constraints that each terminal and root participates in at most one added edge and that $A(G')$ is nilpotent, i.e., the modified graph remains acyclic. The optimum compiled width is $n-\alpha$, where $\alpha$ is the maximum number of such admissible reuse edges [2310.11021].

A third family of models couples reuse to hardware mapping and routing. In modular architectures, the circuit interaction graph $G_c=(V_c,E_c)$ is mapped onto a hardware connectivity graph $G_h=(V_h,E_h)$ of cores or QPUs. Per-slice allocation is represented by binary variables $x_{t,q,c}$ indicating whether logical qubit $q$ is assigned to core $c$ at time slice $t$. The primary optimization objective is the negative inter-core communication reward
$$
R = -\sum_{t=1}^{T-1}\sum_{q=1}^{Q}\sum_{c_1=1}^{C}\sum_{c_2=1}^{C}
x_{t,q,c_1}\cdot x_{t+1,q,c_2}\cdot D_{c_1,c_2},
$$
where $D$ is the distance or cost matrix over cores. For reuse selection, QARMA-R evaluates candidate pairs with
$$
\begin{split}
cost(q_1,q_2) = &\; w_0 \cdot \Delta depth + w_1 \cdot last\_idx(q_1) \\
& + w_2 \cdot |last\_idx(q_1)-first\_idx(q_2)|,
\end{split}
$$
with default $w_0=w_1=w_2=1$ [2506.09323].

These formalisms differ in emphasis—compiled width, acyclicity, SWAP count, inter-core movement, or latency—but they share a common semantic core: a legal reuse plan is a temporally ordered reassignment of logical qubits to a smaller pool of physical resources, constrained by quantum dependencies and enabled by measurement-reset boundaries.

## 3. Compilation methodologies

The compiler literature divides broadly into exact optimization, structured heuristics, learned policies, and post-reuse dynamic-operation simplification. Exact qubit-reuse compilation was formalized in both a constraint programming model and a greedy heuristic that use causal cones of measured outputs. The CP-SAT model introduces binary variables for whether a qubit is measured at a given step and whether a logical qubit remains required up to that step; the greedy method selects the next output whose causal cone adds the fewest new inputs beyond the union of cones already activated. The same work introduces dual circuits, obtained by exchanging state preparations with measurements and reversing time, and shows that optimal qubit-reuse compilation requires the same number of qubits to execute a circuit as its dual [2210.08039].

GidNET replaces global optimization with a candidate-matrix-driven graph heuristic. It repeatedly selects an available terminal, grows a reuse sequence using common-neighbor intersections,
$$
N_x = \bigcap_{q_k \in T_x} P_k,
$$
and breaks ties with the reuse score
$$
I_j = \sum_{k \ne j;\, q_k \in M} |N_j \cap N_k|.
$$
Randomized multi-start with approximately $\lceil \log n \rceil$ iterations improves solution quality while maintaining polynomial scaling. The resulting dynamic circuit is emitted by inserting measure/reset operations between logical qubits in each reuse sequence and rebinding them to a smaller set of virtual qubits [2410.08817].

In modular systems, QARMA and QARMA-R move beyond width minimization to joint allocation, routing, and reuse. Their encoder combines GNN embeddings for local interaction structure with transformer layers for long-range temporal dependencies, using scaled dot-product attention,
$$
\text{Attention}(Q,K,V)=\text{softmax}\!\left(\frac{QK^\top}{\sqrt{d_k}}\right)V,
$$
with sinusoidal and relative positional encodings, 8 heads, model dimension $d=256$, and $N=3$ layers in encoder and decoder stacks. The decoder uses masked self-attention and pointer attention to output a probability over cores for the current qubit; action masks enforce capacity and friend-qubit co-location constraints. Training uses REINFORCE with a greedy rollout baseline from RL4CO, Adam optimizer $(10^{-4})$, batch size 512, and 100 epochs with dynamic data generation each epoch [2506.09323].

A complementary line of work attempts to remove the runtime cost of dynamic operations after reuse decisions have been made. The optimization framework for reducing mid-circuit measurements and resets extends the Probabilistic Circuit Model to multi-qubit states via circuit synthesis, adds reset elimination, and uses Quantum Constant Propagation to identify measurement or reset sites that can be replaced by static unitary constructions. Its two constructive transformations are a measurement-on-entanglement replacement using an extended probabilistic gate
$$
G_{\mathcal P}[(U_1,p_1),\dots,(U_k,p_k)]
$$
and a reset-on-entanglement replacement using
$$
T_{\psi \to \phi} := SP_{|\phi\rangle}\cdot SP_{|\psi\rangle}^{-1}.
$$
The pass thereby removes $t_{meas}$, $t_{reset}$, and $t_{feedforward}$ from the runtime while accepting extra synthesized unitary structure [2504.16579].

A later development extends reuse beyond reorder and reset by moving measurements through commuting structure, replacing quantum-controlled gates with classically controlled gates, and using the deferred measurement principle to unlock reuse in circuits where reorder+reset alone fails. In that formulation, diagonal gates commute with $M_Z$, bit-flip gates induce classical negation of the recorded bit, and controlled operations can be turned into classical-feedforward operations whenever the control is no longer needed coherently. The reported effect is that QPE can be reduced to $Q_{dyn}=2$ and QFT to $Q_{dyn}=1$, whereas reorder+reset alone cannot reduce qubits for those families [2511.22712].

## 4. Architectural models and hardware constraints

Dynamic reuse is inseparable from hardware timing, measurement fidelity, reset quality, and controller latency. In modular quantum architectures, the assumed hardware is often a set of interconnected QPUs with all-to-all connectivity inside each chip and much costlier operations across chips. QARMA and QARMA-R, for example, evaluate a modular system of 10 chips organized in a $2\times5$ grid, each chip having 10 physical qubits with all-to-all intra-chip connectivity, and model inter-core transfers through a distance matrix $D$ that captures the relative cost, latency, or error of moving a quantum state between cores. The reward function then directly penalizes changes of core assignment across time slices [2506.09323].

Real-time classical communication can itself extend reuse semantics across multiple QPUs. In the demonstration of dynamic circuits spanning two Eagle QPUs, a central processor collects mid-circuit measurement outcomes and broadcasts branch selections to control instruments, enabling conditional gates on one QPU based on measurements on another. The additional switch latency is of the order of $0.5\,\mu s$ and is independent of the selected case. The system uses staggered dynamical decoupling and zero-noise extrapolation to suppress static ZZ errors during the conditional-control window, and it creates graph states on 103 and 134 qubits, while the abstract states that the method employs up to 142 qubits spanning multiple QPUs connected in real time with a classical link [2402.17833].

Error heterogeneity under frequent mid-circuit measurement has motivated explicitly MCM-aware compilers. MERA begins with lightweight profiling: for each qubit, it runs 1,024 shots of $|0\rangle \to X \to |1\rangle \to$ MCM with reset $\to$ Measure, thereby estimating a per-qubit $Err_{MCM}(q)$. On IBM Eagle (127q) and Heron (156q), these MCM error distributions remain largely stable for $\ge 24$ hours. MERA then incorporates $Err_{MCM}$ into layout, routing, and scheduling, using an error-aware seed score, a SABRE-derived layout cost, a hierarchical SWAP ranking that considers remaining MCM intensity, and ALAP scheduling with context-aware dynamic decoupling such as XY4, XY8, and CPMG [2511.10921].

Reset quality is itself highly variable and state-dependent. The optimal reuse framework that jointly models mapping and reuse characterized resets on ibmq\_ehningen and found the reset fidelity to be state-dependent and to range, depending on the reset qubit, from 67.5% to 100% in a near-term quantum computer. The runtime placement stage therefore uses a decoherence-adjusted reset fidelity
$$
\xi_{r,p}=e^{-\epsilon_{r,p}/T}\cdot(1-\mathcal{R}_{r,p}),
$$
and a global cost
$$
\mathrm{cost}(\bar{a},\xi,R_p)=1-\prod_{g_x\in C}\xi_{g_x}\prod_{r_p\in C}\xi_{R_p,p},
$$
so that reuse decisions are not separated from device-specific calibration [2308.00194].

## 5. Representative applications and empirical results

The most direct benchmark axis is width reduction. GidNET reports a consistent reduction in compiled circuit widths by a geometric mean of 4.4%, reaching up to 21% in larger circuits when compared with QNET, together with average execution time reduction of 97.4% and up to 99.3%. Against Qiskit reuse, it achieves an average improvement of 59.3%, with maximum reductions of up to 72% in the largest tested circuits. The paper’s five-qubit worked example reduces $W_{orig}=5$ to $W_{comp}=2$, yielding $r=(5-2)/5=60\%$ [2410.08817].

On modular hardware, reuse affects not only width but communication structure. QARMA-R reduces inter-core communications by up to 100% and on average 85% across benchmarks relative to Qiskit (v1.4.0, optimization level 3), and many circuits reach zero inter-core transfers under QARMA-R. For larger circuits, reported examples include multiplier-n15 $(48 \to 13)$, ising-model-13 $(70 \to 22)$, ising-model-16 $(70 \to 20)$, square-root-n18 $(239 \to 134)$, and multiplier-n45 $(1,045 \to 251)$. Against QUBO mapping, QARMA-R achieves 96.7–100% reductions versus QUBO across benchmarks, while even QARMA without reuse yields 96.4–100% reductions on large random circuits [2506.09323].

Early experimental work on IBM heavy-hex devices emphasized the routing and fidelity side of reuse. Using compiler-assisted reuse with mid-circuit measurement and reset, Bernstein–Vazirani circuits showed circuit resource usage can be improved by 60\%, and circuit fidelity can be improved by 15\%. The same study reports resource usage reductions by up to 80\% and circuit fidelity by up to 20\%, with the caveat that aggressive reuse can also increase duration and therefore decoherence. In the BV examples, reuse avoided weak qubits and reduced or eliminated SWAP insertion, which was the mechanism behind the measured fidelity gains [2211.01925].

Reuse also composes naturally with other circuit-reduction strategies. QRCC jointly optimizes qubit reuse and circuit cutting, exploiting the fact that wire cuts create temporal gaps that expose additional reuse opportunities. For distribution-output circuits, it reduces wire cuts by 34% on average (IQRC-C) and 32% (IQRC-B). For expectation-value circuits with gate cuts, it reduces the effective number of cuts by 25–28% on average. In a real-machine validation on IBM Lagos, QRCC split a REG instance into two subcircuits with 1 wire cut and 1 gate cut; the reported accuracies were 22.3% for direct 7-qubit device execution, 92% for shot-based simulation, and 98.3% for QRCC [2312.10298].

Qubit reuse is also useful in quantum error correction. In the honeycomb Floquet code, a dynamic circuit measures gauge operators without ancillas by shrinking each two-body operator onto a data qubit, measuring it, and resetting it. Under circuit-level depolarizing noise, the reported thresholds are $p_{th}^D \approx 0.29\%$ for the dynamic circuit and $p_{th}^A \approx 0.21\%$ for the standard ancilla circuit. At a physical error rate of $10^{-3}$, the dynamic circuit needs distance $d=28$ to reach $p_L \approx 10^{-12}$, corresponding to about 4,700 qubits, while the standard circuit needs $d=52$, corresponding to about 13,500 qubits. The paper therefore estimates a nearly $3\times$ reduction in the number of qubits required to reach a $10^{-12}$ logical error rate [2507.08069].

Finally, dynamic reuse has been demonstrated at system scale. Qubit-reuse compilation with mid-circuit measurement and reset experimentally realized an 80-qubit QAOA MaxCut circuit on the 20-qubit Quantinuum H1-1 trapped-ion quantum processor, thereby showing that causal-cone-based reuse can support circuits far beyond the native device width while preserving the target measurement distribution [2210.08039].

## 6. Limitations, controversies, and open directions

The central trade-off is between reduced qubit footprint and increased dynamic overhead. Mid-circuit measurements, resets, classical branching, and added serialization can elongate the critical path. The optimization framework for reducing mid-circuit measurements and resets explicitly models this as
$$
T = \sum t_{gates} + \sum t_{meas} + \sum t_{reset} + \sum t_{feedforward},
$$
and seeks to reduce $\Delta T$ by replacing dynamic operations with static synthesis when possible. Likewise, the early IBM-heavy-hex study observed that excessive measure-reset operations increase $T$, so that some highly compressed variants underperform moderate-reuse designs in fidelity [2504.16579] [2211.01925].

Noise-awareness remains incomplete in many reuse compilers. QARMA and QARMA-R optimize primarily for minimizing inter-core transfers, while a fully noise-aware fidelity model is identified as future work. MERA argues that compilers such as the Qiskit compiler and QR-Map do not account for pronounced qubit-dependent MCM variability, and shows fidelity improvement of 24.94%–52.00% over the Qiskit compiler (optimization level 3) without introducing additional overhead on 27 benchmark circuits. This tension suggests that reuse decisions, mapping, and scheduling cannot be treated independently on hardware where measurement-induced crosstalk, idling during reset, and reset infidelity dominate [2506.09323] [2511.10921].

There are also theoretical and algorithmic open questions. The exact graph-based optimization for dynamic compilation is strongly related to maximum acyclic subgraph reasoning, and the literature treats optimal formulations as computationally hard. Generalization across hardware models is unresolved: several papers note that scalability to very different topologies, to fault-tolerant regimes, or to strongly adaptive programs remains open. Compilers that optimize width alone may be suboptimal once routing, device heterogeneity, or controller limits are included; conversely, highly expressive dynamic-circuit transformations can create substantial depth overhead even while reducing width dramatically [2310.11021] [2308.00194] [2511.22712].

Recent extensions indicate that “reuse” need not be limited to measure-then-reset on superconducting or trapped-ion qubits. One direction replaces hardware reset by unitary rewinding: for convolutional tensor-network circuits, partially time-reversing the idle region can return a subset of qubits exponentially close to $|0\ldots0\rangle$ without mid-circuit measurement or reset, with reset fidelity bounded by an exponential decay in the number of reversed layers [2012.01676]. Another direction develops optical reset with classical memory in self-looped interferometers, where a time-bin mode is reused across many steps and the stored measurement history reduces the uncertainty of future outcomes; in the 50:50 case, the event-history mutual information reaches approximately 0.7 bits and the single-step entropy saturates to approximately 1.96 bits [2509.02980]. A plausible implication is that dynamic circuit-based reuse is becoming a broader theory of temporally multiplexed quantum resources rather than a single compiler pass tied to one hardware family.

Taken together, the literature presents dynamic circuit-based qubit reuse as a mature but still rapidly evolving compilation discipline: it has exact graph-theoretic foundations, multiple practical heuristics, learned policies for modular systems, hardware-aware extensions for MCM-dominated noise, and concrete demonstrations on NISQ processors and error-correcting codes. What remains unsettled is not whether reuse is useful, but how best to co-optimize it with topology, latency, measurement quality, and downstream algorithmic structure.

Source: https://www.emergentmind.com/topics/dynamic-circuit-based-qubit-reuse