---
title: Double Duty Logic Block Architecture
url: https://www.emergentmind.com/topics/double-duty-logic-block-architecture
type: topic
---

# Double Duty Logic Block Architecture

The **Double Duty logic block architecture** is an FPGA logic-block modification proposed for a **Stratix-10-like architecture** to enable the **concurrent use of the adders and LUTs within a logic element**. In the baseline organization assumed by the work, adder-chain inputs are driven by LUT outputs, so one logic element can usually use either its LUTs for logic or its LUTs together with the carry chain for arithmetic-related logic, but not a LUT function and an unrelated adder-chain function at the same time. Double Duty breaks that coupling by introducing direct adder-feed inputs that bypass the LUT fabric while preserving the original logic-block input count and global routing organization. The named architecture is presented in two variants, **DD5** and **DD6**, with **DD5** identified as the main proposal and the better practical point [2507.11709].

## 1. Baseline architectural setting

The starting point for Double Duty is a **Stratix-10-like FPGA architecture**, modeled in VTR using a prior open-source Intel-like architecture. At the cluster level, a logic block contains **10 ALMs** (Adaptive Logic Modules), a programmable **local crossbar** connects logic-block inputs to the ALM inputs, and adjacent ALMs are linked by dedicated carry-in and carry-out connections to form long fast arithmetic chains [2507.11709].

A single baseline ALM contains **four 4-input LUTs**, fracturing and multiplexing logic so that those LUTs can be combined into **two 5-input functions** or **one 6-input function**, **two 1-bit full adders**, and output multiplexing. The decisive structural detail is that the **inputs of the full adders are driven by LUT outputs**. In effect, the baseline dataflow is local crossbar to ALM inputs **A–H**, then the LUT network, then the full adders and carry chain, and finally the outputs. The adder therefore exists physically inside the ALM, but it is not independently addressable as a routing target [2507.11709].

At the logic-block boundary, global routing and direct neighboring logic-block links feed **connection block muxes**, which in turn drive **60 LB inputs**. Of these, **40 LB inputs can be connected to LB-to-LB direct links**. The local crossbar inside the logic block is relatively rich—**more than 50% populated**—and each of the 10 ALMs draws its ordinary inputs from this interconnect. This baseline offers substantial local flexibility for LUT-based logic, but not for independently routable adder inputs [2507.11709].

## 2. Architectural problem and the Double Duty modification

The central problem identified by the Double Duty work is that modern FPGA logic elements structurally couple two useful primitives. Because the adder inputs are fed by LUT outputs, using the **adder chain** consumes LUT resources to produce the adder operands, while using the **LUTs for unrelated logic** prevents the adder from being independently fed by arbitrary signals. The paper characterizes this as a limitation on arithmetic density, synthesis freedom, and packing efficiency, particularly for arithmetic-heavy and irregular workloads such as **sparse DNNs**, **mixed-precision arithmetic**, and **unrolled DNN inference** [2507.11709].

The proposed solution introduces two architectural changes. The first is an **AddMux inside each ALM** together with **four new ALM inputs** labeled **\(Z_1\)–\(Z_4\)**. These inputs allow selected signals to **bypass the LUTs** and connect directly to adder-chain inputs. The second is a secondary local interconnect at the logic-block level, called the **AddMux Crossbar**, which sources signals from the existing logic-block inputs and feeds the new direct adder-bypass paths. The paper emphasizes that **no extra cluster/LB input pins are added**, **global routing is unchanged**, and the architecture reuses the same logic-block inputs already present in the baseline [2507.11709].

The architecture defines two variants. **DD5** supports concurrent **5-LUT + adder** use. **DD6** extends the same principle to concurrent **6-LUT + adder** use by modifying output multiplexing further, but the paper reports that DD6 adds extra output-mux complexity and yields only marginal practical benefit [2507.11709].

A concrete structural feature is the sparsity of the new adder-bypass interconnect. The AddMux Crossbar taps **10 of the existing 40 candidate LB inputs** that can receive direct LB-to-LB signals, out of **60 total LB inputs**, so its population is:

$$
\frac{10}{60}
$$

which the paper states is **17% populated**. This is much sparser than the conventional local crossbar and therefore constrains direct-adder operand selection relative to ordinary LUT input selection [2507.11709].

## 3. Concurrent LUT and adder use inside one ALM

The defining property of Double Duty is that one ALM can carry out two productive sub-uses in parallel. In **DD5**, adder operands can arrive through **\(Z_1\)–\(Z_4\)**, bypassing the LUTs, while the LUT fabric remains available for independent logic. The paper specifies the output allocation in this mode as **O1 and O3** for **adder outputs** and **O2 and O4** for **5-LUT outputs**. A single DD5 ALM can therefore simultaneously contribute **two arithmetic outputs from the full adders** and **two logic outputs from 5-LUT functions** [2507.11709].

This decoupling is the basis for the architecture’s claim of higher effective logic density. The adder hardware and LUT hardware already coexist physically in the same ALM in the baseline architecture; Double Duty changes the connectivity so that they can be used **concurrently and independently** rather than being forced into a mutually dependent relationship. The intended gain is strongest in circuits where arithmetic and unrelated control or Boolean logic coexist within the same local packing neighborhood [2507.11709].

The modified logic block also changes the internal routing model. The cluster now contains **two internal interconnect fabrics**: the conventional, richer local crossbar for normal LUT inputs and a smaller sparse **AddMux Crossbar** for direct adder feeds. The ordinary ALM inputs remain **A–H**, while **\(Z_1\)–\(Z_4\)** denote the new direct inputs into the adder path. This separation preserves the baseline LUT-input path while adding a second, bypass-oriented path into the arithmetic fabric [2507.11709].

The paper presents DD6 as a further extension of the same idea. DD6 preserves the bypass mechanism but changes output multiplexing so that a **6-LUT** can also operate concurrently with the adders. However, the evaluation indicates that current CAD does not exploit this mode well and that only about **7% of ALMs** in the benchmarks use **6-LUT mode** on average, which helps explain the limited utility of DD6 in the reported experiments [2507.11709].

## 4. CAD model, synthesis support, and formal definitions

The Double Duty evaluation is not restricted to an abstract architectural sketch. The architecture was modeled in **VTR (Verilog-to-Routing)** for end-to-end CAD, with **Parmys/Yosys** as front-end synthesis and **COFFE 2** for transistor-level area and delay modeling. The authors extended the baseline Stratix-10-like architecture with **AddMux**, **AddMux Crossbar**, and modified output muxing for DD5 and DD6. Timing models for the new components were obtained from **COFFE 2** after SPICE modeling and transistor sizing [2507.11709].

The experimental flow used **timing-driven placement**, **timing-driven routing**, and **three random seeds per experiment, averaged**. The architecture parameters included **10 ALMs per LB**, **channel width = 400**, and `target_ext_pin_util = 0.9` for both inputs and outputs, allowing the VTR packer to use up to **90%** of LB I/O pins [2507.11709].

The paper also strengthened the arithmetic synthesis baseline. It added **unrolled multiplication optimizations**, **improved binary adder-tree synthesis**, and **compressor tree synthesis**. One cited example is that for an **8-bit multiplication by constant \((01010101)_2\)**, baseline VTR used **2.85×** more full adders than optimal. The improved binary-adder-tree synthesis uses a dynamic-programming row-pairing strategy guided by the strength heuristic

$$
H_S = I_S / O_S
$$

where \(H_S\) is the strength of a candidate solution \(S\), \(I_S\) is the number of input signals included by the adder chains in that stage, and \(O_S\) is the number of output signals generated by that stage. Final experiments used **Wallace** reduction because it gave the best overall results [2507.11709].

This stronger CAD baseline matters for interpretation of the architectural gains. The paper reports that the updated arithmetic synthesis improved VTR’s area-delay product by roughly **37%** on **Kratos** versus baseline VTR, with resource use close to **Intel Quartus**, which suggests that the reported Double Duty improvements are not an artifact of a weak reference flow [2507.11709].

## 5. Quantitative results, benefits, and trade-offs

At the circuit-component level, the hardware overhead of DD5 is modest but nonzero. The paper reports **AddMux** area of **1.698 MWTAs** with delay **68.77 ps**, **AddMux Crossbar** area of **77.91 MWTAs** with delay **77.05 ps**, a **Baseline ALM** area of **2,167.3 MWTAs**, and a **DD5 ALM** area of **2,366.6 MWTAs**, corresponding to a **+3.72%** ALM area increase. The baseline crossbar area and delay are **289.6 MWTAs** and **72.61 ps**, respectively [2507.11709].

The timing impact is asymmetric. In the baseline, **LB input \(\rightarrow\) ALM inputs A-H** is **72.61 ps**, and **ALM inputs A-H \(\rightarrow\) Adder input** is **133.4 ps**. In Double Duty, **LB input \(\rightarrow\) ALM inputs \(Z_1\)-\(Z_4\)** is **77.05 ps**, which is **+6.11%** relative to baseline LB-to-A-H, while **ALM inputs A-H \(\rightarrow\) Adder input** becomes **202.2 ps**, or **+51.6%** relative to the baseline A-H-to-adder path. By contrast, **ALM inputs \(Z_1\)-\(Z_4\) \(\rightarrow\) Adder input** is **68.77 ps**, which is **-48.4%** relative to the baseline A-H-to-adder path. This means that the bypass path is materially faster for adder inputs when it is actually used, while the old LUT-fed adder path becomes slower [2507.11709].

Across benchmark suites, the main reported architecture-level result for **DD5 vs baseline** is an **average ALM area reduction across all benchmarks of 10.9%**. The paper reports **21.6%** area reduction on **Kratos**, **9.3%** on **Koios**, and **8.2%** on **VTR**, with the **average critical path delay remaining at the same level as baseline**. Some circuits show up to **16% delay increase**, but the **average area-delay product improvement across all circuits** is **9.7%** [2507.11709].

The benchmark suites differ materially in arithmetic intensity. The paper evaluates **19 VTR circuits** with average **10.2k ALMs** and average adder percentage **19.5%**, **20 Koios circuits** with average **64.3k ALMs** and average adder percentage **22.5%**, and **7 Kratos circuits** with average **59.6k ALMs** and average adder percentage **61.4%**. The much larger gain on Kratos is therefore consistent with the architecture’s intended focus on adder-intensive designs [2507.11709].

The reported trade-offs are explicit. Denser packing shifts routing channel utilization upward, particularly in the **0.3 to 0.6** utilization range on Kratos, indicating more congestion. Nevertheless, **none of the circuits failed to route**. DD6 provides only **minor additional area savings** on Kratos, **no noticeable gains** on Koios or VTR, and incurs an average **frequency penalty of about 8%**, yielding worse area-delay product. The paper therefore positions DD5, not DD6, as the practical sweet spot [2507.11709].

Stress tests reinforce the same interpretation. In a synthetic circuit with **500 adders** and increasing numbers of **5-LUTs**, practical concurrent LUT-and-adder occupancy saturated at **375**, which is **75% of the theoretical maximum**. In an end-to-end fixed-capacity experiment, **conv1d-FU-mini** increased from **5** to **9** maximum SHA instances, **conv2d-FU-mini** from **3** to **5**, and **gemmt-FU-mini** from **11** to **13**, with concurrent 5-LUT counts of **4397**, **2458**, and **3790**, respectively [2507.11709].

## 6. Related and indirect interpretations of “double duty” logic blocks

The term **Double Duty logic block architecture** is used explicitly for the FPGA proposal just described, but the broader idea of a logic block serving more than one architectural role appears in other contexts with different emphases. A useful comparison is **qBSA**, a **32-bit Block-Skewed RSFQ Arithmetic Logic Unit**, which the paper itself does **not** describe using Double Duty terminology. The qBSA work instead proposes a **block-skewed datapath** in which a 32-bit operand is divided into **eight 4-bit blocks**, and least-significant blocks are accepted and completed earlier than more significant blocks. Each 4-bit block is a multifunction ALU slice supporting **ADD, SUB, SLT, EQ, AND, OR, XOR, and NOR**, and the architecture uses mechanisms such as **\(C_{out\_early}\)** and a **feedback path from the output of each block back to its input** so that a subsequent data-dependent operation can start after the pipeline depth of a **4-bit ALU block (8-clock stages)** rather than the full **32-bit ALU (15-clock stages)** [2001.10715].

That comparison is indirect rather than terminological. qBSA can be read as exhibiting a “double duty”-like organization because the same 4-bit block supports arithmetic and Boolean functions, generates carry for the next block, and also anchors earlier temporal feedback for dependent recurrence. However, the qBSA paper frames its contribution as **temporal skewing for dependent-operation throughput**, not as an explicitly named dual-function logic-block doctrine [2001.10715].

A stronger conceptual analogue at the device level appears in work on **digital logic using 3-terminal spin transfer torque devices**. That paper demonstrates that a single **3-terminal element** formed by an **MTJ** and an **STT element** with a **shared free magnetic layer** can implement functionally complete digital logic. In that architecture, logical states are represented as **output resistances** that **retain their state when unpowered**, and the same physical element simultaneously acts as a **storage node**, a **logic output**, and a **threshold evaluator** during clocked operation. The same topology can realize **buffer/inverter**, **AND/NAND**, and **OR/NOR** behavior by changing pinned-layer orientation and threshold conditions [1101.3222].

These related cases clarify the scope of the Double Duty concept. In the FPGA paper, “double duty” refers specifically to enabling one logic element to use **LUTs and dedicated adders concurrently** through direct adder-input bypass. In the RSFQ and spintronic cases, the analogous dual-role behavior is architectural or device-level rather than a named FPGA logic-block mechanism. The common thread is not a single universal formalism, but a recurring design strategy: increasing effective density or functionality by allowing one physical structure to perform more than one useful role without duplicating the primitive [2507.11709].

Source: https://www.emergentmind.com/topics/double-duty-logic-block-architecture