---
title: Distributed Sparse Ising Machine (DSIM)
url: https://www.emergentmind.com/topics/distributed-sparse-ising-machine-dsim
type: topic
---

# Distributed Sparse Ising Machine (DSIM)

The Distributed Sparse Ising Machine (DSIM) is a scalable probabilistic computing platform implemented by networking multiple Field-Programmable Gate Arrays (FPGAs) to sample from and optimize Ising models significantly exceeding single-chip resource and memory constraints. Leveraging programmable “p-bits,” each node in the DSIM collectively builds a distributed architecture that performs Gibbs sampling at multi-trillion flip-per-second rates, maintaining all coupling weights and biases in local on-chip memory and minimizing inter-device communication to 1-bit exchange per boundary spin. The DSIM provides a programmable and empirical platform for advancing stochastic optimization and sampling, with demonstrated applications in spin glass physics, Max-Cut, and Boolean satisfiability, and establishes quantitative design rules for partitioned machine accuracy and throughput [2606.25313].

## 1. System Architecture and Block-Level Organization

Each DSIM node consists of an FPGA implementing a “partition” of a global sparse Ising graph. Within each FPGA:

- Local on-chip memories store all intra-partition couplings $J_{ij}$ and p-bit biases $\theta_i$; no weights traverse the interconnect.
- Banks of programmable p-bits ($N_{\rm p-bit}$), e.g., $\approx50,000$ p-bits/FPGA for $37^3$ lattices or $\approx13,900$ p-bits/Super Logic Region for $100^3$ lattices.
- P-bits within each partition are divided into $N_{\rm color}$ independent color groups via graph coloring to facilitate parallel update of all p-bits in a given group.
- Multiple FPGAs are interconnected in a sparse, boundary-only communication topology (e.g., 6-device chains in DSIM-1 or 18-board rectangles in DSIM-2). Within each FPGA, further sub-partitioning (along Super Logic Region boundaries) with “shadow-weight” duplication addresses extremely large graphs.

The partitioning scheme ensures that all memory-intensive aspects of the Ising graph are handled locally; inter-FPGA traffic only consists of minimal p-bit boundary information for edges linking partitions.

## 2. Gibbs Sampling and P-bit Update Rule

Each p-bit $i$ maintains a state $s_i \in \{+1, -1\}$. Updates utilize Gibbs sampling:

$$
P[s_i = +1] = \sigma(2\beta h_i) = (1 + e^{-2\beta h_i})^{-1}
$$

with the local field

$$
h_i = \sum_j J_{ij} s_j + \theta_i,
$$

where $\beta$ is the inverse temperature and $\sigma(x) = (1 + e^{-x})^{-1}$. Alternatively, one may sample via

$$
s_i = \operatorname{sgn}[\tanh(\beta h_i) + r]
$$

with $r \sim U(-1, +1)$. The probabilistic logic is mapped directly onto hardware, with color-group parallelism determining which p-bits can be flipped simultaneously without update conflicts.

## 3. Partitioned Communication and the Timing Ratio $\eta$

After graph partitioning, each cross-partition edge duplicates its $J_{ij}$ (“shadowed”) onto both participant FPGAs. At runtime, only the state $s_i$ and $s_j$ for boundary p-bits must be exchanged, comprising 1 bit per direction per edge. The p-bits in non-boundary regions remain strictly local.

Two key clock domains govern DSIM performance:

- $f_{\rm p-bit}$: the local p-bit update rate (spin flips per second, per p-bit)
- $f_{\rm comm}$: boundary-bit transfer rate

The single dimensionless parameter

$$
\eta = \frac{f_{\rm comm}}{f_{\rm p\text{-}bit}}
$$

regulates the staleness of boundary p-bit data and, consequently, the system’s effective fidelity to the unpartitioned (monolithic) Ising sampler.

A conservative design rule prohibits local updates from overtaking boundary refreshes:

$$
f_{\rm p\text{-}bit} \leq \frac{f_{\rm comm}}{2\,N_{\rm color}\,C_{\max}} \equiv f_{\rm p\text{-}bit,max},
$$

where $N_{\rm color}$ is the number of color groups and $C_{\max}$ is the maximum congestion (worst-case boundary-traffic factor). System performance saturates to the monolithic case when

$$
\eta \gtrsim 2 N_{\rm color} C_{\max}.
$$

For example, in a $L^3 = 37^3$ system with $N_{\rm color} = 3$ and $C_{\max} \approx 50.8$, the threshold is $\eta_{\rm threshold} \approx 305$.

## 4. Universality of Partitioning Tradeoff: Cluster Mean-Field Theory

The system’s critical throughput-accuracy tradeoff is captured by parallel cluster mean-field theory (CMFT), mapping each FPGA partition to a “cluster.” Within a cluster, full Gibbs sampling is executed locally, but boundary spins of adjacent clusters are held fixed at their mean field averages for $S$ sweeps, then updated.

Given $m_i^{(t)} \in \{\pm1\}$ (state of boundary spin $i$ at sweep $t$):

$$
\langle m_i \rangle = \frac{1}{S} \sum_{t=1}^S m_i^{(t)}.
$$

Cluster $A$ then computes fields using these mean boundaries until the next exchange.

Here, $S$ (exchange interval) is the analog of $1/\eta$ in hardware: $S=1$ ($\eta \to \infty$) gives monolithic equivalence; large $S$ (small $\eta$) induces greater staleness. Empirically and in simulation:

- Frequent exchange ($\eta \gg \eta_{\rm th}$ or $S \sim 1$): residual energy decays with exponent $\kappa_f$ matching ground truth (e.g., $\kappa_f \approx 0.27$).
- Infrequent exchange ($\eta < \eta_{\rm th}$, $S \gg 1$): the decay exhibits a smoothly reduced exponent $\kappa_f(\eta)$.

A one-parameter rescaling collapses hardware and mean-field results onto a universal curve, demonstrating the intrinsic nature of this partition-induced tradeoff in stochastic dynamics.

## 5. Quantitative Performance Metrics and Throughput-Accuracy Curves

The DSIM’s computational throughput is expressed as:

$$
\mathrm{flips/s} = N_{\rm total} \times f_{\rm p\text{-}bit},
$$

with $N_{\rm total}$ the global p-bit count. Empirical results for two configurations:

| System    | FPGAs | $N_{\rm total}$ | $f_{\rm p\text{-}bit}$ | Flips/sec               | $\kappa_f$ (slope)          |
|-----------|-------|-----------------|------------------------|-------------------------|-----------------------------|
| DSIM-1    | 6     | $50,653$        | $0.10$ MHz             | $5.1 \times 10^9$       | $0.264$ (GPU: $0.2693$)     |
|           |       |                 | $50$ MHz (overclocked) | $2.53 \times 10^{12}$   | $0.229$                     |
| DSIM-2    | 18    | $10^6$          | $1$ MHz                | $10^{12}$               | $0.282$ (GPU: $0.2836$)     |
|           |       |                 | $3$ MHz (overclocked)  | $3 \times 10^{12}$      | $0.2565$                    |

Time-to-target analysis shows “easy” targets (higher residual energy $\rho_E^\star \gtrsim 0.01$) benefit from overclocking (up to hundreds-fold speedup), while for ultra-low $\rho_E^\star$ the accuracy cost (reduced $\kappa_f$) outweighs throughput, with the crossover dictated by slopes and flip-rate ratio.

## 6. Empirical Demonstrations and Applications

DSIM has demonstrated performance across diverse problems:

- **3D Edwards–Anderson Spin Glasses**: DSIM and monolithic GPU reference systems yield identical power-law exponents ($\kappa_f \approx 0.27$ for $37^3$, $0.283$ for $100^3$). Overclocked DSIMs manifest the predicted $\eta$-controlled exponent reduction.
- **Max-Cut (Gset G81, 20,000 nodes)**: Augmented with adaptive parallel tempering and isoenergetic cluster moves, DSIM-1 at $f_{\rm p\text{-}bit} = 1\,\mathrm{MHz}$ achieves the certified-optimal cut (14,060), with a 14% hit rate, matching leading heuristic and exact solvers.
- **Boolean Satisfiability (3SAT, near phase transition)**: For $n = 13,042$ variables and $m = 55,558$ clauses (mapped to $250,011$ p-bits with invertible logic/copy gates), DSIM-2 at $0.5\,\mathrm{MHz}$ matches GPU progress up to $10^9$ sweeps, reaching $99.74\%$ clause satisfaction.

The architecture’s ability to preserve solution quality hinges on maintaining $\eta$ above the partition-dependent threshold. If $\eta$ drops below this threshold, the residual energy decay exponent decreases, introducing a quantifiable and predictable throughput-accuracy tradeoff managed at system configuration time.

## 7. Scaling Implications and Design Rules

DSIM demonstrates that scaling probabilistic computers for Ising models beyond single-chip limitations is feasible when all couplings remain strictly local and only minimal state information is exchanged across partitions. The dimensionless timing ratio $\eta$ provides a tunable handle for system designers: above the threshold $\eta_{\rm th} \approx 2 N_{\rm color} C_{\max}$, partitioning is transparent and the system is mathematically indistinguishable from its monolithic counterpart; below, solution quality degrades in a quantitatively predictable manner. Cluster mean-field theory verifies the universality of this throughput-accuracy tradeoff, supplying a quantitative design framework for partitioned stochastic systems at scale [2606.25313].

Source: https://www.emergentmind.com/topics/distributed-sparse-ising-machine-dsim