---
title: Crossbar Arrays & Memory-Compute Co-location
url: https://www.emergentmind.com/topics/crossbar-arrays-and-memory-compute-co-location
type: topic
---

# Crossbar Arrays & Memory-Compute Co-location

Crossbar arrays are nanoscale or microscale structures in which programmable memory devices are arranged at the intersection of perpendicular lines (“wordlines” and “bitlines”), enabling both high-density data storage and in-place analog or digital computation. Memory-compute co-location refers to architectural strategies that perform the majority of computational operations directly within the memory array—particularly multiply-accumulate (MAC) operations using Ohm’s and Kirchhoff’s circuit laws—effectively collapsing the logic and memory units into a unified physical fabric. This removes the von Neumann bottleneck by eliminating energy-expensive data shuttling between memory and ALU, providing orders-of-magnitude improvements in energy per MAC, latency, and on-chip storage density for neural network inference and other tasks [2206.08735, 2411.04814, 2509.10627].

## 1. Physical Structure and Computational Model of Crossbar Arrays

Each crossbar cell consists of a memory device (e.g., RRAM, FeFET, PCM, MRAM, SRAM, or ferroelectric diode) whose conductance $G_{ij}$ encodes a weight or logical state at the intersection of row $i$ and column $j$. Input voltages $V_i$ are applied to wordlines, and the resulting currents $I_{ij} = G_{ij} V_i$ are summed along bitlines, implementing analog MVM operations in one step (vector-matrix multiply: $\vec{I}_{\text{col}} = G \cdot \vec{V}_{\text{row}}$) [2206.08735, 2411.04814, 2307.04261]. For signed weights, a differential encoding scheme with pairs of devices per entry is used: $w_{ij} \propto G_{ij}^+ - G_{ij}^-$ [2601.07086, 2004.03073].

Key peripheral circuits include:

- Input DACs to generate analog voltages from digital activations.
- Output ADCs to digitize bitline sums.
- Row/column selectors, drivers, and local control logic for address decoding and experiment orchestration.

The co-location of memory (weight storage) and compute (MAC) physically in the same array tile is fundamental. All multiply-accumulate operations occur “where the data reside,” without transferring weights off-array [2206.08735, 2411.04814].

## 2. Memory-Compute Co-location: Architectures and System Design

Memory-compute co-location is instantiated at various spatial scales:

- **Array and Tile Level Co-location**: Each crossbar tile integrates memory cells, periphery for conversion (DAC/ADC), and minimal logic. Matrix-vector multiplications for DNN inference proceed within the tile, without off-tile data movement [2411.04814, 2312.04261].
- **Hierarchical Integration**: Large arrays are partitioned into tiles or “M-Cores”; each can be dynamically re-configured as memory, arithmetic unit, or neuromorphic processor [1612.02913].
- **Peripheral Resource Optimization**: Sharing ADC/DACs, customized bit-slicing, and dynamic switching strategies are essential peripheral co-design elements for high utilization and optimal energy/area trade-offs [2411.04814, 2509.10627].

In digital and analog modes, crossbar tiles support population-count operations, logic (e.g., MAGIC NOR/NOT gates), and MVMs [1612.02913, 2009.00881].

The following table summarizes representative device types and co-location features:

| Memory Device   | Native Mode      | Suitability for Co-location                    |
|-----------------|------------------|-----------------------------------------------|
| ReRAM (1T-1R)   | Analog/digital   | High density, multilevel, moderate variation  |
| FeFET           | Analog/digital   | Small cell, robust scaling, high RHRS/RON     |
| PCM             | Analog           | Fast, multilevel, drift/variation challenges  |
| MRAM            | Digital          | High endurance, binary, limited scaling       |
| SRAM (8T)       | Digital          | High ON/OFF, large cell, sensitive to IR drop |

[2307.04261, 2408.05857, 2206.08735]

## 3. Technology and Circuit Non-Idealities: Scaling, Robustness, and Remedies

While memory-compute co-location realizes massive data-movement reduction, system-level performance and accuracy hinge on a nuanced balance among device, circuit, and architecture design:

- **Wiring Non-idealities**: Line resistance (high in scaled nodes) induces IR drops, distorting MAC linearity. Techniques such as row-bit agglomeration (SWANN) and Partial Wordline Activation (PWA) mitigate these errors and restore DNN accuracy [2406.14706, 2408.05857].
- **Device Variability and Noise**: Stochastic and systematic variations (e.g., conductance drift in PCM, resistive state dispersion in ReRAM, switching noise in FeFET) degrade computational fidelity. Model-based compensation (MLP emulation, hardware-aware training) and controlled refresh are necessary [2004.03073, 2601.07086].
- **Peripheral Overhead**: ADC/DAC design dominates area and energy for high-precision (e.g., 8+ bits). Dynamic and shared architectures (dynamic-switch ADCs [2509.10627], custom reference thresholds [2408.05857]) are employed to optimize accuracy/energy under sparsity.
- **Selector-Free or Selector-Based Designs**: Advanced devices (e.g., AlScN FE diodes) exploit rectification and exponential I–V to suppress sneak paths without selectors, supporting high scaling and temperature robustness [2506.05452].

## 4. Mapping, Packing, and Utilization: Algorithmic and Architectural Strategies

Efficient mapping of neural networks or logic onto crossbar arrays is critical for maximizing utilization and minimizing area/latency.

- **Bin Packing and Fragmentation**: Neural-network layers are split into sub-blocks matched to tile capacities. Packing algorithms (greedy, integer programming) account for tile aspect ratio, fragmentation, and peripheral scaling. Minimum-tile count and minimum-area optima do not always coincide due to inter-tile and periphery trade-offs [2411.04814].
- **Pipeline vs. Dense Packing**: Pipeline packing enables low-latency inference at the cost of increased area; dense packing minimizes area but may elongate critical paths [2411.04814].
- **Correlation-Aware Mapping**: Application-specific dataflow (e.g., in DLRM embedding reduction) exploits co-occurrence graphs and access statistics for grouping, duplication, and adaptive crossbar usage, boosting effective utilization (>85% in ReRAM crossbars with ReCross) [2509.10627].
- **Block Allocation and Synchronization**: For parallel fabrics, dataflow-aware allocation (e.g., block-based array assignment for ResNet-18) sustains utilization >90%, yielding 7.47× speedup over naïve allocation [2008.06741].

## 5. Quantitative Gains: Energy, Throughput, and System-Level Impact

Empirical and modeled results demonstrate the profound impact of crossbar-based memory-compute co-location:

- **Energy per MAC**: In analog mode, per-MAC energy is reduced by up to 100× versus digital SRAM, subject to peripheral overheads and sharing [2411.04814, 2206.08735].
- **Throughput and Latency**: Single-cycle MVM enables O(1) time per input vector; practical designs achieve up to 10× faster inference than digital systolic arrays for large N [2004.03073, 2307.14557].
- **Utilization and Mapping Efficiency**:

  | Optimization            | Utilization | Performance Gain                    |
  |-------------------------|-------------|-------------------------------------|
  | Naïve mapping           | 25–40%      | Baseline                            |
  | Correlation-aware (ReCross) | >85%    | 3.97× faster, 6.1× energy efficiency|
  | SWANN + PWA (128×128 SRAM)  | 88.8%   | Accuracy from 47.8% → 88.8%         |

  [2509.10627, 2406.14706, 2008.06741]

- **Selector-Free Arrays**: 128×128 AlScN FE-diode crossbars achieve 2500 bits/mm², energy per MAC ~1 nJ for 128-term VMM, and robust operation up to 600 °C [2506.05452].

## 6. Application Domains and Extension to General Computing

Beyond DNN inference:

- **In-Memory Reduction and Sparse Operations**: ReRAM crossbars in ReCross eliminate DRAM-CPU bottlenecks for large recommendation models by processing reductions in situ, with adaptive ADC switching [2509.10627].
- **Polynomial Modular Multiplication**: X-Poly maps Conv1D directly into crossbars, achieving up to 200× speedup over CPUs for cryptographic PMM [2307.14557].
- **Digital and Analog Logic**: Magic-style logic (e.g., NOR, NOT) can be implemented in memristive crossbars, with mapping tools such as CONTRA optimizing area-delay product for Boolean circuits [2009.00881].
- **Hybrid Electrical-Optical Computing**: Plasmonic nonvolatile crossbars enable dual electrical-optical VMM, sub-10 fJ/MAC energy, and ultrahigh throughput, representing a path towards three-dimensional, mixed-signal neuromorphic hardware [2107.05424].

## 7. Co-Design and Future Prospects

A convergence of device, circuit, and system-level co-design is necessary. Key principles include:

- Co-optimizing array size, aspect ratio, and peripheral circuit scaling for each workload [2411.04814, 2408.05857].
- Developing robust device models, calibration protocols, and system-level emulation tools (e.g., XBTorch) to bridge device non-idealities and algorithmic requirements [2601.07086, 2004.03073].
- Advancing 3D-integration strategies to realize higher density, peripherally efficient architectures [2206.08735, 1612.02913].
- Algorithm-device co-optimization (training with noise/drift awareness, error correction, quantization strategies) to tolerate and even exploit hardware non-idealities [2601.07086].

A major direction is extending in-memory compute beyond neural inference to general-purpose workloads, as demonstrated in reconfigurable fabrics (FPCA) and in-memory logic frameworks (CONTRA), suggesting increasing scope for memory-compute co-location across the computational stack [1612.02913, 2009.00881].

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**References**:  
- [1612.02913] Field-Programmable Crossbar Array (FPCA) for Reconfigurable Computing  
- [2206.08735] A Co-design view of Compute in-Memory with Non-Volatile Elements for Neural Networks  
- [2307.04261], [2408.05857], [2411.04814], [2509.10627] Comparative and mapping studies  
- [2004.03073], [2601.07086] Device-level modeling and emulation  
- [2406.14706], [2506.05452] Robustness and selector-free design  
- [2307.14557], [2107.05424], [2008.06741], [2009.00881] Applications, utilization, and digital/optical extension

Source: https://www.emergentmind.com/topics/crossbar-arrays-and-memory-compute-co-location