---
title: CMOS-Compatible On-Chip RIS for mm-Wave Systems
url: https://www.emergentmind.com/topics/cmos-compatible-on-chip-reconfigurable-intelligent-surface-ris
type: topic
---

# CMOS-Compatible On-Chip RIS for mm-Wave Systems

A CMOS-compatible on-chip reconfigurable intelligent surface (RIS) is a millimeter-wave (mm-Wave) metasurface structure directly integrated within a silicon-based microelectronic process, capable of dynamically manipulating incident electromagnetic fields via phase and amplitude control at each subwavelength unit cell. Leveraging standard back-end-of-line (BEOL) foundry processes, these surfaces enable highly dense, energy-efficient, and digitally addressable platforms for applications in 6G mm-Wave communication, short-range imaging, and sensing. Recent experimental demonstrations utilize phase-delay line architectures incorporating phase-change materials, ensuring both low insertion loss and full BEOL compatibility, with wafer-scale integration and scalability to large arrays [2602.23345, 2512.18854]. 

## 1. Unit-Cell Architecture and Principle of Operation

The fundamental building block of a CMOS-compatible on-chip RIS is a phase-delay line unit cell comprising thin-film metallization and dielectrics atop a high-resistivity silicon substrate. The canonical topology consists of:

- **Top Layer:** A patterned copper slot (width $w_s$, length $l_s$, thickness ~1 μm), acting as a frequency-selective aperture that couples incident W-band fields into the cell.
- **SiO₂ Dielectric Spacer:** Thickness $h_{SiO₂} = 15\,μm$, serving to isolate and suppress parasitic conduction into the silicon substrate and facilitate the guided-wave network.
- **Delay-Line Layer:** Copper microstrip ($w_d = 30\,μm$, $l_d = 400\,μm$), interrupted by a vanadium dioxide (VO₂) film (~100 nm thick) precisely patterned by lift-off lithography.
- **Ground Plane:** Continuous copper on high-resistivity ($\rho>1\,kΩ\cdot$cm) silicon ($h_{Si}=300\,μm$) suppresses substrate loss and supports dense two-dimensional tiling.

Within each cell, the VO₂ segment modulates the effective electrical length of the guided path. In the insulating (OFF) state, current traverses a longer, high-impedance route, whereas in the metallic (ON) state, VO₂ forms a low-impedance bridge, enabling a shorter path. This results in two quantized phase states, with a design target phase shift at the resonance frequency $f_0 \approx 100.75\,$GHz:
$$
Δφ = φ_{\text{ON}} - φ_{\text{OFF}} = ω_0Δτ = π
$$
The unit cell is modeled as a frequency-dependent surface impedance,
$$
Z_s(ω) = R + j\left(ωL - \frac{1}{ωC}\right),
$$
with the corresponding reflection coefficient
$$
Γ(ω,φ) = \frac{Z_s(ω,φ) - η_0}{Z_s(ω,φ) + η_0},
$$
where $η_0 \approx 377\,Ω$ is the free-space impedance. Measured reflection magnitude satisfies $|Γ| > 0.75$ (–1.2 dB) for both phase states [2512.18854].

| State   | |S₁₁| (Simulated, dB) | Phase (°) | $Δφ$ (°) |
|---------|----------------------|-----------|----------|
| OFF     | –1.1                 | 0         | 180      |
| ON      | –1.0                 | 180       | –        |

## 2. Array Design, Beam Steering, and System Performance

A prototype array comprises $60\times60$ unit cells on a $1.125$ mm pitch, forming a $67.5\,$mm aperture. Free-space illumination with a W-band horn at incidence angle $θ_{inc}=30^\circ$ demonstrates beam-steering via programmed binary phase patterns. Each cell is thermally switched via micro-heaters, permitting row/column-specific biasing.

The overall array factor (AF) is written as:
$$
AF(θ,ϕ) = \sum_{m=1}^{60}\sum_{n=1}^{60} e^{j[k(x_m\sinθ\cosϕ + y_n\sinθ\sinϕ) + φ_{mn}]}
$$
with $φ_{mn}∈\{0,π\}$. Steering is achieved by applying spatially progressive phase patterns across the surface. For $Δφ=π$ with $d ≈ 0.23λ_0$, main-beam angle $θ\approx ±46^\circ$.

| Metric                    | Simulated | Measured  |
|---------------------------|-----------|-----------|
| Main-lobe angle (°)       | 0         | 0         |
| FWHM (°)                  | 3.2       | 3.5       |
| Side-lobe level (dB)      | –12.5     | –11.8     |
| ON/OFF enhancement @0°(dB)| —         | 27.1      |

Measured results yield array gain of 14.5 dBi at broadside and a 27.1 dB ON/OFF contrast [2512.18854]. Insertion loss per unit cell is ~1.2 dB. Owing to device quantization (1-bit), side-lobe levels and angular resolution follow digital reflectarray theory.

## 3. Frequency Response and Calibration

The slot-line structure introduces dispersion, with phase difference $Δφ(ω)$ maintained at 180° only within a finite bandwidth ($\sim0.4\,$GHz ≈ 0.4%). Outside the ±200 MHz band around $f_0$, $Δφ$ degrades by >20°. In wideband OFDM systems, compensation schemes include:

- Subcarrier-specific baseband pre-distortion to correct for frequency-dependent phase response.
- Calibration with swept test tones on individual RIS elements to generate corrected codebooks.
- For true wideband flattening, additional tunable LC/varactor layers are needed, though not implemented in the reported design [2602.23345].

## 4. CMOS Process Integration and Fabrication

The RIS-on-chip fabrication is strictly compliant with standard BEOL flows using only copper and SiO₂:

1. 300 μm high-resistivity Si starting wafer.
2. Blanket 200 nm Cu ground plane deposition.
3. Copper phase-delay line lithography, Cu sputter, and lift-off.
4. PECVD SiO₂ of 1.5–15 μm for isolation.
5. VO₂ thin film (100–200 nm) deposited and patterned by lift-off on designated segments.
6. Final photolithography, Cu sputtering, and patterning for slot layer.
  
No deep reactive ion etching (DRIE) or non-CMOS-compatible steps are involved. VO₂ is integrated as a thin layer below thermal budget constraints (<200 nm, <400°C), supporting full monolithic or flip-chip co-packaging with mm-Wave transceiver dies [2512.18854, 2602.23345].

## 5. Control, System-Level Integration, and Calibration

- **Addressing**: Individual cells are controlled by local micro-heater drivers activated via a low-frequency serial bus (SPI-like), enabling independent or group control of VO₂ switching.
- **Packaging**: The architecture supports wafer-scale integration or flip-chip assembly with redistribution-layer (RDL) interconnects for digital biasing.
- **Mutual Coupling Calibration**: Due to dense subwavelength tiling ($d ≈ 0.23λ_0$), mutual coupling induces non-diagonal S-matrices. Factory calibration measures the $N\times N$ coupling matrix, leading to the effective codebook:
  $$
  Γ_{eff} = (I – S)^{-1} \operatorname{diag}\{Γ_i\}
  $$
  Calibration may be maintained by periodic pilot tones or over-the-air feedback, closing the loop via baseband DSP adjustment [2602.23345].
- **Multi-tile Coordination**: Large reflectarray apertures can be formed by networking multiple RIS-on-chip tiles, mapping global beamforming commands to local VO₂ bias states.

## 6. Performance Metrics, Trade-offs, and Limitations

| Parameter              | Value                             |
|------------------------|-----------------------------------|
| Insertion loss         | ~1.2 dB/cell @ $f_0$              |
| Reflectarray bandwidth | ~0.4 GHz (Δf/$f_0$ ≈ 0.4%)        |
| Phase quantization     | 1-bit ($Δφ=180°$)                 |
| Element spacing        | $d ≈ 0.23λ_0$                     |
| Power per transition   | ~10 mW (pulse, VO₂ heater)        |
| Switching speed        | ~100 ns (VO₂ thermally-driven)    |
| Footprint              | $d\times d = (0.23 λ_0)^2$        |

Higher phase quantization (multi-bit) is feasible via additional VO₂ segments but increases complexity and cell size. Trade-offs exist between angular resolution (smaller $d$ preferable), mutual coupling (exacerbated by dense tiling), and control granularity. Power consumption is dominated by transient heating pulses for VO₂, with negligible static current. Key scalability considerations include: 

- Thermal cross-talk between adjacent VO₂ heaters.
- Long-term reliability of VO₂ phase cycling (>10⁶ cycles reported).
- Moving toward seamless electronic addressing without external feeds [2512.18854].

## 7. Applications and Outlook

CMOS-compatible on-chip RIS solutions enable monolithic or tightly-co-packaged integration with W-band (100 GHz-class) 6G transceiver front-ends. Potential application domains include:

- Dynamic wireless environment shaping (beam-forming, reflection, spatial filtering) for 6G indoor and short-range communication systems.
- Adaptive mm-Wave imaging, sensing, and localization platforms exploiting compact, low-power metasurface arrays.
- Hybrid systems utilizing both RIS and traditional phased-array modules for combined analog and digital beam-forming.

Current research emphasizes robust system-level calibration methodologies, tile-wise coordination, enhanced phase resolution, wideband operation, and further reduction of insertion loss [2602.23345, 2512.18854]. A plausible implication is that continued material-process innovations (thin-film VO₂, alternative phase-change materials) and advanced control architectures will underpin future scalable, CMOS-integrated RIS deployments.

Source: https://www.emergentmind.com/topics/cmos-compatible-on-chip-reconfigurable-intelligent-surface-ris