---
title: 'CircuitGPS: Multi-Domain Circuit Systems'
url: https://www.emergentmind.com/topics/circuitgps
type: topic
---

# CircuitGPS: Multi-Domain Circuit Systems

In the cited arXiv literature, **CircuitGPS** refers to several technically distinct systems rather than a single unified method. The name is used for a graph-based analog-circuit diagram retrieval pipeline, a few-shot graph-learning framework for parasitic-capacitance prediction in analog/mixed-signal (AMS) netlists, a precision-timing overlay on high-voltage transmission networks intended as a GNSS alternative, and several embedded GPS-centered vehicle tracking or intrusion-control implementations [2503.11658] [2507.06538] [2307.14495] [1904.09838] [1803.08325] [2004.04864]. Across these usages, the commonality is not application domain but the coupling of circuit structure with localization, timing, or retrieval objectives.

## 1. Terminological scope

The most precise way to treat the term is as a **shared label across multiple research threads**. In one thread, CircuitGPS retrieves analog-circuit diagrams by converting them into hierarchical graphs and ranking matches with graph-edit-distance (GED). In another, CircuitGPS is a few-shot learning method for parasitic-effect prediction in AMS circuits, using heterogeneous netlist graphs, subgraph sampling, and a GraphGPS-style encoder. In a third, CircuitGPS denotes a wired precision-timing network over electrical transmission grids, where chirp spread-spectrum signals disseminate time in a way intended to replace or back up GNSS. Separate implementation-oriented descriptions further use the label for GPS-enabled embedded systems in vehicle tracking and geolocation [2503.11658] [2507.06538] [2307.14495] [1904.09838] [1803.08325].

| Usage | Core object | Representative paper |
|---|---|---|
| Circuit diagram retrieval | Hierarchical graph of devices, pins, and nets | [2503.11658] |
| AMS parasitic prediction | Heterogeneous netlist graph with coupling links | [2507.06538] |
| GNSS alternative timing | Chirp-based timing over PLC channels | [2307.14495] |
| Embedded GPS systems | NMEA/UART/GSM/FPGA vehicle platforms | [1904.09838], [1803.08325], [2004.04864] |

A common misconception is to assume that all uses refer to GNSS or vehicle positioning. The literature does not support that reading. The graph-based uses are about circuit representation and retrieval or prediction, whereas the timing and vehicle systems are literal GPS or GNSS-related systems. This suggests that “CircuitGPS” functions primarily as a project name reused in different subfields, not as a stable acronym with a single accepted expansion.

## 2. Graph-based retrieval of analog-circuit diagrams

In "Circuit Diagram Retrieval Based on Hierarchical Circuit Graph Representation" [2503.11658], CircuitGPS is a retrieval system for analog-circuit diagrams that treats the problem as **graph retrieval** rather than conventional image retrieval. The pipeline has two phases: **Circuit Diagram Recognition** and **Hierarchical Graph Retrieval**. The recognition stage takes an RGB diagram image, performs object detection with an attention-augmented YOLOv8 model called **GAM-YOLO**, and then extracts topology via a **2-step connected domain filtering algorithm**. The retrieval stage builds two graph representations and applies a coarse-to-fine GED-based search.

GAM-YOLO inserts a **Global Attention Module (GAM)** between the neck and head. Feature maps \(P_1, P_2, P_3\) are reweighted by channel and spatial attention in series,
$$
F_{\text{out}} = F_{\text{in}} \odot M_c(F_{\text{in}}) \odot M_s(F_{\text{in}}).
$$
The head uses **VariFocal Loss (VFL)** for classification and **Distribution Focal Loss (DFL)+CIoU** for localization. On a **2 048 + 227 circuit-diagram dataset (23 304 labeled symbols)**, GAM-YOLO achieves **precision=0.914, recall=0.907, mAP＠50=0.902** [2503.11658].

Topology extraction first converts the image to grayscale with
$$
GRAY=0.299R+0.587G+0.114B
$$
and binarizes using **Otsu for light backgrounds** and the **Triangle method for dark** backgrounds. The first connected-domain filter removes domains smaller than **10 % of total pixels** to eliminate text and noise. The second removes any domain that does not intersect a detected component’s bounding box. By intersecting filtered net blobs with symbol boxes, the system recovers **pin-to-net connectivity**.

The retrieval stage uses two graph levels. The **Class-1 (Device-only) graph** has device symbols as nodes, with an edge between two devices if they share at least one net. The **Class-4 (Device-plus-Pin) graph** augments device nodes with pin nodes and uses edges both from devices to pins and between pins that are wired together. Node types are encoded as one-hot vectors \(x_v \in \mathbb{R}^C\), and connectivity is represented by adjacency matrix \(A\), where \(A_{uv}=1\) if \((u,v)\in E\), else \(0\).

Similarity is computed via **normalized graph-edit-distance**,
$$
nGED(G_1,G_2)=\frac{GED(G_1,G_2)}{((|V_1|+|V_2|)/2)},
$$
and converted to
$$
S(G_1,G_2)=\exp(-nGED(G_1,G_2)).
$$
GED is computed via an **A*-based search [48]**. Stage 1 computes \(S\) on Class-1 graphs and keeps the **top 20**. Stage 2 recomputes \(S\) on these candidates using Class-4 graphs and returns the **top 5** final matches [2503.11658].

On the retrieval dataset of **503 diagrams across 10 circuit families**, the reported **AP＠5 / avg. time/query** values are as follows:

| Retrieval setting | AP＠5 | Avg. time/query |
|---|---:|---:|
| Class-1 only | 0.815 | 47.6 s |
| Class-4 only | 0.881 | 252.1 s |
| Hierarchical (Class-1→Class-4) | 0.881 | 57.9 s |

The baselines are **ResNet101+FC+cosine (mAP≈0.529)**, **VGG16+SVD+QE (mAP≈0.627)**, and **VGG16+PCA+QE (mAP≈0.416)**. The paper identifies three principal advantages: **topology-aware** discrimination, **flexible fidelity** through coarse and fine graphs, and a **plug-and-play** retrieval stage in which any GED or subgraph-matching engine can be used. Its stated limitations are equally explicit: GED remains **NP-hard**, edge labels are omitted in the prototype, and future work could weight “critical” blocks such as **differential pairs** more heavily [2503.11658].

## 3. Few-shot learning for AMS parasitic-capacitance prediction

In "Few-shot Learning on AMS Circuits and Its Application to Parasitic Capacitance Prediction" [2507.06538], CircuitGPS is a **few-shot learning method** for predicting parasitic effects in AMS circuits. The input is an AMS circuit netlist cast as a **heterogeneous, undirected graph**
$$
G=(V,E),\quad \mathbf{X}=\{x_i\}_{i\in V},\;\mathbf{E}=\{e_{ij}\}_{(i,j)\in E}.
$$
Each node carries
$$
x_i\in\{0,1,2\}=\{\text{net},\,\text{device},\,\text{pin}\},
$$
and each schematic edge carries
$$
e_{ij}\in\{0,1\}=\{\text{device–pin},\,\text{net–pin}\}.
$$
Coupling relations to be predicted are represented as additional link types,
$$
e_{ij}\in\{2,3,4\}=\{\text{pin–net},\,\text{pin–pin},\,\text{net–net}\},
$$
with every node also receiving a secondary attribute vector \(x^C_i\in\mathbb R^{d_C}\), such as transistor widths or counts of connected devices. The full graph is written as
$$
G=\bigl(V,\;E\cup R,\;(\mathbf{X},\mathbf{X}_C,\mathbf{E})\bigr).
$$

A central design choice is **small-hop enclosing subgraph sampling**. Given a target link \((m,n)\), CircuitGPS extracts an \(h\)-hop enclosing subgraph \(G^h_{m,n}\) defined by
$$
V^h_{m,n}=\{\,i\in V\mid d(i,m)\le h\;\vee\;d(i,n)\le h\},
$$
with edges restricted accordingly. In practice, the paper states that **\(h=1\) suffices**, both for efficiency and because of theoretically guaranteed \(\gamma\)-decay of high-order heuristics from **SEAL [Zhang & Chen ’18]**. Negative samples for link-prediction pre-training are constructed as **structural negatives** by endpoint permutation while preserving node-type compatibility.

The encoder follows the **GraphGPS recipe [Rampášek et al. ’22]**, interleaving an edge-aware MPNN with a global Transformer block. For layer \(\ell\),
$$
\bigl(X_M^{\ell+1},E^{\ell+1}\bigr)=\mathrm{MPNN}_e^\ell(X^\ell,E^\ell,A),
$$
$$
X_A^{\ell+1}=\mathrm{GlobalAttn}^\ell(X^\ell)=\mathrm{softmax}(QK^\top/\sqrt{d_k})V,
$$
and
$$
X^{\ell+1}=\mathrm{MLP}^\ell(X_M^{\ell+1}+X_A^{\ell+1}).
$$
Residual connections and batch normalization are applied after each block. Circuit-statistic vectors \(x^C_i\) are projected or embedded into \(\mathbb R^{d_L}\) and added before global pooling and the task-specific MLP head [2507.06538].

To inject positional information with low overhead, the method defines **double-anchor shortest-path distance (DSPD)**:
$$
\mathrm{DSPD}(i)=\bigl(d(i,m),\,d(i,n)\bigr)\in\mathbb Z^2.
$$
These distances are embedded via learned look-up tables and concatenated with the node-type embedding to form
$$
X^0=[\mathbf{D}_0\|\mathbf{D}_1\|\mathrm{Embed}(x)].
$$
The training pipeline has two stages. Pre-training minimizes binary cross-entropy for link prediction,
$$
L_{\rm link} =-\frac1{|\mathcal P|+|\mathcal N|} \sum_{(i,j)\in\mathcal P\cup\mathcal N} \Bigl[y_{ij}\log\hat p_{ij} + (1-y_{ij})\log(1-\hat p_{ij})\Bigr],
$$
with negatives balanced across **\(p\!-\!n\), \(p\!-\!p\), \(n\!-\!n\)** coupling types. Fine-tuning minimizes mean absolute error for capacitance regression,
$$
L_{\rm reg}=\frac1{|\mathcal P|+|\mathcal N|}\sum_{(i,j)}|\hat c_{ij}-c_{ij}^{\rm true}|.
$$

On three unseen benchmarks—**DIGITAL_CLK_GEN**, **TIMING_CONTROL**, and **ARRAY_128_32**—CircuitGPS achieves **zero-shot link-existence accuracies of 0.980–0.989 versus 0.72–0.76 for ParaGraph/DLPL-Cap**, described as a **≥20 pp improvement**. In capacitance regression, it reduces **MAE from ≈0.15 to ≈0.08 (a drop ≥0.067)**. The ablation results further show that **DSPD yields the best accuracy (0.9618) at low cost (0.017 s/subgraph)**, and that a pure **GatedGCN MPNN** matches or slightly outperforms the MPNN+Transformer hybrid while requiring less compute [2507.06538].

## 4. Precision timing over electrical transmission grids

In "A GPS Alternative using Electrical Transmission Grids as Precision Timing Networks" [2307.14495], CircuitGPS is a **precision-timing overlay on existing high-voltage transmission networks**. It replaces or backs up GNSS by transmitting **time-synchronised chirps** over **power-line carrier (PLC)** channels and recovering **1 PPS** ticks through high-resolution chirp cross-correlation. The system has a **calibration stage**, when GNSS is available and a remote substation measures the one-way time-of-flight (TOF), and an **implementation stage**, when GNSS is unavailable and the substation reconstructs the correct 1 PPS by subtracting the previously measured TOF from the received-chirp timestamp.

The transmitted linear chirp is modeled as
$$
s(t)=A\exp\bigl[j(2\pi f_0 t+\pi k t^2)\bigr],\quad 0\le t<T,
$$
with instantaneous frequency \(f(t)=f_0+kt\) and \(k=B/T\). The theoretical timing resolution is on the order of \(1/B\). For instance, **\(B=100\) kHz yields a fundamental resolution of \(\sim10\,\mu s\)**, while interpolation and larger bandwidths support sub-\(\mu s\) accuracy.

Delay estimation is based on maximizing the cross-correlation of \(r(t)=s(t-\tau)+n(t)\) with a local chirp copy,
$$
\hat\tau=\underset{\tau}{\arg\max}\;R_{rs}(\tau).
$$
Rather than direct sliding-window correlation, the method **dechirps** the received signal and performs a single \(N\)-point FFT, reducing complexity from \(O(N^2)\) to \(O(N\log N)\). Fine interpolation is performed through \(s\) dechirp shifts of \(\delta=T/s\), yielding
$$
c(i+hN)=\sum_{n=0}^{N-1}\bigl[r(n\Delta+h\delta)e^{-j\pi k(n\Delta+h\delta)^2}\bigr]e^{-j2\pi i n/N},
$$
and
$$
\hat\tau=(\arg\max_m c(m))\times \frac{\Delta}{s}.
$$
The paper states that modern CSS engines on FPGAs or DSPs can compute **\(>10^5\)** such correlations per second [2307.14495].

The network architecture consists of a **central substation transmitter** with a GNSS-disciplined timing module, chirp generator, upconversion to a PLC carrier around **\(\sim100\)–300 kHz**, and a **capacitive coupling network (TACS)**; and **remote substation receivers** with coupling taps, bandpass and low-noise amplification, ADC-to-FPGA chains, FFT processing, arg-max logic over fine-shifted bins, moving-average filtering, and timing reconstruction. A laboratory prototype uses **\(N=1024\)**, **\(s=32\)**, **\(B=327.68\) kHz**, and **\(T=3.125\) ms**, implemented on a **Xilinx FPGA** with a **65 MSPS DAC/ADC pair** [2307.14495].

ATP-EMTP simulations on the **UK L6 extra-high-voltage network** use **JMarti frequency-dependent line models**. Chirps of **81.92 ms**, **\(B=100\) kHz**, **\(N=2^{13}=8192\)**, and **\(s=100\)** are injected via a custom C++ foreign model. Noise is modeled by an **\(\alpha\)-stable process** plus clipping of impulses above threshold. The signal-to-dispersion ratio is defined as
$$
\mathrm{SNR}_D=10\log_{10}\frac{P_{\rm signal}}{2\gamma^2}.
$$
Monte Carlo runs show **sub-\(\mu s\) timing standard deviation for \(\mathrm{SNR}_D\ge -10\) dB**, **\(\sigma_\tau\approx250\) ns at \(\mathrm{SNR}_D=0\) dB**, and insensitivity to impulsiveness down to **\(\alpha=1.6\)**. The error variance is stated to track the linear-FM Cramér–Rao bound,
$$
\operatorname{Var}(\hat\tau)\approx \frac{1}{8\pi^2 B^2\,\mathrm{SNR}},
$$
with further averaging over \(M\) chirps reducing noise by \(1/\sqrt{M}\) [2307.14495].

In laboratory testing over a **700 m RG58 coax** with delay **\(\approx3.7\,\mu s\)**, the recovered 1 PPS maintains **sub-\(\mu s\) RMS timing error down to an SNR of –20 dB**. The paper further notes that **EHV aerial modes attenuate only \(0.1\) dB/km at hundreds of kHz**, so national-scale deployment is presented as plausible if averaging times and per-link SNR budgets are properly managed [2307.14495].

## 5. Embedded GPS and vehicle-security implementations

A separate group of CircuitGPS usages concerns **embedded GPS-centered systems** for vehicle tracking, geolocation filtering, and intrusion response. These systems are distinct from the graph-based retrieval and AMS-learning lines because they operate on NMEA streams, UART links, GSM modules, microcontrollers, or FPGA SoCs rather than graph matching or subgraph representation learning.

In the FPGA-based **GPS Vehicle Tracking SoC** described by **Yaqzant, Damaj, and Zantout** [1904.09838], the top-level architecture includes a **GPS RF/IF front end**, **NMEA parser & ASCII-to-binary converter**, **coordinate computation engine**, **soft-core microcontroller subsystem**, **memory interface & data buffering**, and **I/O control & RF transceiver interface**. In the NMEA-only mode, the GPS module outputs ASCII at **9600 baud**; a UART deserializer feeds a FIFO; a parser FSM scans for **“\$GPRMC”** or **“\$GPGGA”**; field delimiters select time, latitude, longitude, speed, and date; and an ASCII-to-binary converter handles **ddmm.mmmm** conversion. On an **Altera Stratix-EP1S10F484C5**, reported utilization is **~6 000/10 570 LUTs (57%)**, **~6 350/10 570 FFs (60%)**, **38 BRAMs**, and **2 DSPs**. Compared with a **PIC18F4620 + external UART + I²C** baseline, the FPGA-SoC reports **~17 μs per sentence** parsing latency versus **~3–5 ms**, **≥50 Hz** sustained sampling versus **~5 Hz**, **~250 mW** power versus **~120 mW**, and **\$16.80** unit cost versus **\$18.50** at **1000 pcs** [1904.09838].

In the **Arduino + SIM908** geolocation tool [1803.08325], the system centers on an **Arduino-compatible microcontroller board** with a **stackable SIM908 shield** integrating **quad-band GSM/GPRS** and an **integrated GPS L1-band receiver**. The specifications reproduced in the source include **ATmega328P @ 16 MHz, 5 V supply, 32 kB flash, 2 kB SRAM**, and a SIM908 GPS receiver range of **1561.098 MHz–1587.250 MHz** with **−159 dBm tracking sensitivity**. Typical wiring maps **PWRKEY** to **digital pin 8**, and routes **TXD/RXD** to Arduino serial pins. The GPS subsystem streams **GPRMC, GPGGA** and related NMEA sentences at **9600 baud** for downstream parsing and reporting via **HTTP or SMS**. Two filtering methods are applied: a **1-D Kalman filter** with **\(R=1\)** and **\(P_0=4\)**,
$$
K_k=\frac{P_{k-1}}{P_{k-1}+R},\quad
x_k=K_k z_k +(1-K_k)x_{k-1},\quad
P_k=(1-K_k)P_{k-1},
$$
and a **cumulative average filter**
$$
y_k=\frac{1}{k+1}\sum_{i=0}^{k} z_i.
$$
In a **clear-sky outdoor** test in **Ankara, Turkey** with **\(N=30\)** consecutive fixes, reported errors were **9.39 m** raw, **3.64 m** last-error and **3.47 m** minimum-error for the Kalman-filtered output, and **4.18 m** for the average-filtered output [1803.08325].

A related GPS-enabled vehicle intrusion-control system [2004.04864] integrates **Holux GR-89 GPS**, **SIM300CZ GSM**, an **8052 µC (AT89S52 class)**, **Mercury Tilt Switches**, and relay control for gears and engine. The GPS module is wired with **VCC (3.3 V)**, **GND**, **TXD** to **8052 P3.0 (RxD)**, and **RXD** from **8052 P3.1 (TxD)**, using a level shifter if the microcontroller is **5 V**. The GR-89 outputs standard **NMEA-0183** at **4800 bps by default** and is often configurable to **9600 bps**. Firmware listens for **GPRMC**, verifies checksum, parses latitude and longitude, converts from **ddmm.mmmm** or **dddmm.mmmm** to decimal degrees,
$$
decimal\_deg=\left\lfloor\frac{raw}{100}\right\rfloor+\frac{raw-100\lfloor raw/100\rfloor}{60},
$$
and sends location via **AT+CMGF=1** and **AT+CMGS** on the GSM link. The paper-level description states that on intrusion, the owner can respond by SMS to **lock the gears** or **seize the engine** from a far-off place [2004.04864].

| System | Main hardware | Reported outcome |
|---|---|---|
| FPGA vehicle tracking SoC | Stratix FPGA, soft-core CPU, parser, BRAM, UART/I²C | ~17 μs parsing, ≥50 Hz sampling [1904.09838] |
| Arduino geolocation tool | Arduino/ATmega328P + SIM908 | 9.39 m raw to 3.64 m Kalman last-error [1803.08325] |
| Intrusion-control GPS path | 8052 + Holux GR-89 + SIM300CZ | SMS alert and remote gear/engine control [2004.04864] |

These systems are concrete embodiments of GPS-centered embedded design. They are not retrieval engines and do not use graph similarity; instead, they are organized around UART framing, NMEA parsing, RF front ends, relay actuation, and low-cost filtering or hardware acceleration.

## 6. Related quantum-secured GPS and broader implications

A further GPS-related line of work, while not presented as the same system as the graph-based or embedded CircuitGPS variants, is the **device-independent quantum-secured GPS protocol** of [2504.08465]. Its core is a self-test of a genuinely multipartite entangled **five-qubit code** via a Bell-type inequality, then embedding that self-test into a GNSS positioning loop so that tampering spoils the certified Bell violation. The protocol begins with the CHSH functional
$$
I_2=\langle A_0B_0\rangle+\langle A_0B_1\rangle+\langle A_1B_0\rangle-\langle A_1B_1\rangle\le 2
$$
and extends to a five-party Bell functional \(I_5\) whose maximum **\(4\sqrt2+1\)** is certified by a sum-of-squares decomposition. Achieving this maximum self-tests the two-dimensional code space spanned by \(|0_L\rangle\) and \(|1_L\rangle\) [2504.08465].

For GPS authentication, the paper replaces a classical code with a flying encoded state \(\alpha|0_L\rangle+\beta|1_L\rangle\) distributed among **four satellites** and the **receiver**. Before pseudorange use, the parties estimate \(I_5\); if the violation falls below **\(4\sqrt2+1-\delta\)**, the protocol aborts. The paper assumes an adversary can intercept **up to two of the five qubits in any round** and argues that three or more tampered qubits are required to evade detection while preserving encoded data. The five-qubit encoder circuit uses **4 Hadamard gates** and **8 CNOTs**, with depth
$$
d_{1q}=2,\quad d_{2q}=8.
$$
Reported platform comparisons give **\(t_{\rm total}=216\) ns** and **\(F_{\rm circuit}\approx98.4\%\)** for superconducting qubits, versus **\(t_{\rm total}=483\,\mu s\)** and **\(F_{\rm circuit}\approx99.8\%\)** for trapped ions [2504.08465].

This quantum-secured line is methodologically remote from the graph-retrieval and AMS-learning versions of CircuitGPS, but it highlights a recurrent theme across the broader literature: **circuit structure is used not merely as hardware implementation detail, but as a formal object for inference, certification, or control**. In the retrieval and AMS settings, structure is represented as graphs; in the timing-network setting, as a transmission medium with modeled propagation; in the embedded systems setting, as a tightly coupled signal-processing and communication pipeline; and in the quantum-secured setting, as a code space certified by Bell nonlocality. A plausible implication is that the recurrence of the name reflects a shared emphasis on circuit-aware system design, even though the technical content diverges sharply across domains.

Source: https://www.emergentmind.com/topics/circuitgps