--- title: CIM-Tuner Optimization Frameworks url: https://www.emergentmind.com/topics/cim-tuner type: topic --- # CIM-Tuner Optimization Frameworks Searching arXiv for the relevant CIM-Tuner papers to ground the article and disambiguate the term. CIM-Tuner is a name used for two distinct optimization frameworks in contemporary arXiv literature. In one usage, it denotes a portfolio-based hyperparameter-tuning framework for the Chaotic Amplitude Control with momentum (CACm) algorithm in Coherent Ising Machines (CIMs), where the objective is to minimize Time To Solution (TTS) by decomposing a five-dimensional hyperparameter search into sequential one-dimensional subproblems [2507.20295]. In a second usage, it denotes an automatic co-exploration tool for SRAM Computing-In-Memory (CIM) accelerators that jointly balances hardware configuration and layer-wise mapping strategy under an area constraint, targeting throughput or energy efficiency [2601.18070]. A related but differently named framework, CQ-CiM, has also been described as acting as a “CiM-Tuner” for hardware-aware embedding shaping in retrieval systems, but it is not itself titled CIM-Tuner [2602.20083]. ## 1. Terminological scope and disambiguation The term **CIM-Tuner** is not unique to a single research line. It appears in at least two technically separate contexts. | Paper | Domain | Core objective | |---|---|---| | "Towards Generalized Parameter Tuning in Coherent Ising Machines: A Portfolio-Based Approach" [2507.20295] | Coherent Ising Machines | Hyperparameter tuning of CACm via sequential single-parameter optimization | | "CIM-Tuner: Balancing the Compute and Storage Capacity of SRAM-CIM Accelerator via Hardware-mapping Co-exploration" [2601.18070] | SRAM Computing-In-Memory accelerators | Joint hardware balancing and mapping optimization under area constraint | In the first meaning, the framework addresses algorithmic sensitivity in CIM-based combinatorial optimization. The starting observation is that CACm, described as “one of the most accurate solvers on Coherent Ising Machines (CIMs),” is “notoriously sensitive to a high-dimensional set of hyperparameters,” and simultaneous tuning by a single black-box optimizer can be ineffective because of the curse of dimensionality [2507.20295]. In the second meaning, the framework addresses accelerator design and deployment. Here the central problem is the trade-off, under a fixed silicon area budget, between allocating area to the CIM macro array and allocating area to on-chip Input/Output SRAM buffers. Excess compute area can induce frequent off-chip transfers and stalls, whereas excess storage area can reduce peak MAC throughput and under-utilize compute [2601.18070]. A common source of confusion is therefore lexical rather than technical: the same name labels frameworks for two different meanings of “CIM,” namely **Coherent Ising Machines** and **Computing-In-Memory**. This suggests that the term should always be interpreted with its surrounding research context. ## 2. CIM-Tuner for Coherent Ising Machines In the Coherent Ising Machine setting, CIM-Tuner is a hyperparameter-tuning framework for the **Chaotic Amplitude Control with momentum (CACm)** algorithm. It takes as input a baseline parameter vector $$ P_0 = (\beta_1, \beta_2, \alpha, \gamma, \xi), $$ where $\beta_1$ and $\beta_2$ control the decaying damping rate, $\alpha$ is the coupling strength, $\gamma$ the momentum coefficient, and $\xi$ the auxiliary-variable update rate in CACm [2507.20295]. The optimization goal is $$ \min_P TTS(P) \quad \text{subject to} \quad p_i \in [L_i, U_i], \; i=1,\ldots,5, $$ with the formal statement $$ P^* = \arg \min_{P \in D_1 \times \cdots \times D_N} TTS(P). $$ The domains are given as $$ \beta_1,\beta_2 \in [0,2], \qquad \alpha,\gamma \in [0,2], \qquad \xi \in [0,0.3]. $$ The TTS objective is defined by $$ TTS(P) = \frac{\log(1 - 0.99)}{\log(1 - P_0(P))}, $$ where $P_0(P)$ is the empirical probability that a single CACm run with parameters $P$ reaches the ground state, and the constant $0.99$ prescribes 99% reliability [2507.20295]. The framework is motivated by the observation that tuning all CACm parameters simultaneously using a single black-box optimizer, including Bayesian Optimization via TPE, “suffers from the curse of dimensionality: even hundreds of trials fail to yield significant gains” [2507.20295]. CIM-Tuner remedies this by two mechanisms: partitioning the tuning problem into a sequence of one-dimensional subproblems, and embedding a small portfolio of search strategies—TPE, GP, CMA-ES, Random, and Grid—that can be dynamically switched according to each parameter’s characteristics [2507.20295]. The underlying CACm dynamics are also specified. The algorithm evolves a continuous state $x(t)\in\mathbb{R}^n$ and an auxiliary vector $e(t)\in\mathbb{R}^n$ over $T$ time steps. The time-dependent damping is $$ \beta(t) = \beta_1 + \frac{t}{T}(\beta_2 - \beta_1). $$ At each step, $$ x^{t+1} = x^t + \Delta\bigl[-\beta(t)x^t + \alpha e^t \mu^t + \gamma(x^t-x^{t-1})\bigr], $$ $$ e^{t+1} = e^t - \xi(x^{t\,2}-1)e^t, \qquad e^{t+1}\leftarrow \frac{e^{t+1}}{\mathrm{mean}(e^{t+1})}, $$ where $\Delta=0.5$ is the fixed step-size and $\mu^t = W\cdot\tanh(x^t)$ with $W$ the Ising-coupling matrix. The final spin configuration is $\sigma=\mathrm{sign}(x^T)$ [2507.20295]. This formulation makes the role of CIM-Tuner highly specific: it is not a new solver for the Ising Hamiltonian itself, but an auto-tuning layer for a solver whose performance depends strongly on hyperparameter choice. ## 3. Sequential and screened tuning methods in the CIM setting The Coherent Ising Machine version of CIM-Tuner is instantiated as **Method A** and **Method B**. **Method A** is described as **Sequential Single-Parameter Tuning**. It cycles through the $N=5$ hyperparameters in a fixed user-specified order—reported experimentally as $\beta_1 \rightarrow \beta_2 \rightarrow \alpha \rightarrow \gamma \rightarrow \xi$—and dedicates an equal share $T/N$ of the total budget $T$ to each [2507.20295]. At step $k$, all parameters except $p_k$ are fixed at their most recently optimized values, and the optimizer portfolio component $H$ proposes the next value of $p_k$. The procedure is given as: $$ \text{Parameter\_Optimization\_A}(T,N,P^{(0)},M,H): $$ for $k=1\ldots N$, $$ p_k^{(k)} \leftarrow H(\text{target}=p_k,\;\text{fixed}=P^{(k-1)}\setminus\{p_k\},\;\text{trials}=T/N,\;\text{objective } M), $$ then $$ P^{(k)} = (P^{(k-1)}\setminus\{p_k\}) \cup \{p_k^{(k)}\}, $$ and finally it returns $P^*=P^{(N)}$ and $E^*=M(P^*)$ [2507.20295]. **Method B** augments Method A with an initial screening phase. With an initial budget $Y$ per parameter, it independently optimizes each $p_i$ for $Y$ trials and measures the temporary TTS decrease $$ \Delta_i = M(P^{(0)}) - M(P^{(0)} \text{ with } p_i \text{ updated}). $$ These $\Delta_i$ values are sorted in descending order to produce a priority sequence $p_{\sigma(1)},\ldots,p_{\sigma(N)}$, and Method A is then applied on this reordered list using the remaining budget $T-N\cdot Y$ [2507.20295]. The procedure is stated as: $$ \text{Parameter\_Optimization\_B}(T,N,P^{(0)},M,H,Y): $$ for $i=1\ldots N$, $$ p_i^{\mathrm{temp}} \leftarrow H(p_i, P^{(0)}\setminus\{p_i\}, Y, M), $$ $$ \Delta_i = M(P^{(0)}) - M\bigl((P^{(0)}\setminus\{p_i\})\cup\{p_i^{\mathrm{temp}}\}\bigr), $$ then define $\sigma$ so that $$ \Delta_{\sigma(1)} \ge \cdots \ge \Delta_{\sigma(N)}, $$ and call Method A with the reordered parameter sequence [2507.20295]. The conceptual distinction is therefore clear. Method A assumes a fixed order and equal budget partition. Method B uses a lightweight exploratory phase to estimate immediate impact and then imposes an order based on that estimate. The paper states that $Y$ controls the trade-off between ranking accuracy and budget for sequential optimization; the provided practical guideline gives $Y\approx 20$ as an example [2507.20295]. A plausible implication is that Method B is intended to compensate for heterogeneity in parameter sensitivity without returning to fully joint high-dimensional optimization. ## 4. CIM-Tuner for SRAM-CIM accelerators In the SRAM-CIM literature, CIM-Tuner is an automatic tool for **hardware balancing and optimal mapping strategy under area constraint via hardware-mapping co-exploration** [2601.18070]. Its problem formulation is explicitly bi-level in the sense that it simultaneously considers hardware parameters and mapping strategy. The hardware parameter set is $$ {\bf h} = \{MR,\,MC,\,SCR,\,IS\_SIZE,\,OS\_SIZE\}, $$ where $MR\times MC$ is the grid of CIM macros, $SCR$ is the Storage–Compute Ratio per macro, and $IS\_SIZE$ and $OS\_SIZE$ are the capacities of the on-chip input/output SRAMs [2601.18070]. The mapping strategy is $$ \pi = \{\pi_\ell\}, $$ with each layer strategy $\pi_\ell$ represented as the tuple $$ (\text{spatial scheduling},\; \text{temporal scheduling},\; \text{tiling type}). $$ Two optimization objectives are formulated. Throughput maximization is $$ \underset{\bf h,\pi}{\text{maximize}}\quad T({\bf h},\pi)=\frac{\sum_\ell \text{MACs}_\ell}{Lat({\bf h},\pi)} $$ subject to $$ Area({\bf h}) \le A_{\max}, $$ $$ ICW({\bf h}) \ge BW,\qquad WUW({\bf h}) \ge BW, $$ and $$ MR,MC,SCR,IS\_SIZE,OS\_SIZE \in \{2^k\}. $$ Energy-efficiency maximization is $$ \underset{\bf h,\pi}{\text{maximize}}\quad E_{\rm eff}({\bf h},\pi)=\frac{\sum_\ell \text{MACs}_\ell}{Energy({\bf h},\pi)} $$ under the same constraints [2601.18070]. The framework attains generality through a **matrix abstraction of a CIM macro**. A macro is abstracted as a weight matrix of dimension $AL\times PC$ stored in SRAM cells, an input vector of length $AL$, a multiply-accumulate primitive producing a partial-sum vector of length $PC$, and $SCR$ distinct bank-partitions each holding an $AL\times PC$ block [2601.18070]. Two derived parameters are $$ ICW= \begin{cases} AL\times N_{\rm InputBitline}, & \text{digital CIM} \\ AL\times Precision_{DAC}, & \text{analog CIM} \end{cases} $$ and $$ WUW=\frac{\text{number of bits written per cycle}}{1/freq}. $$ The compute latency per $AL$-length input vector is $$ Lat_{\rm compute}=\frac{Datawidth_{\rm in}}{ICW}\times \frac{1}{freq}, $$ and the update latency for a full weight block is $$ Lat_{\rm update}= \frac{AL\times Datawidth_{\rm w}}{WUW}\times \frac{1}{freq} $$ [2601.18070]. At the accelerator level, all designs in the work follow a generalized three-stage template: 1. Input SRAM 2. CIM array 3. Output SRAM Input activations are broadcast along macro columns, partial sums accumulate along macro rows, and off-chip DRAM communicates with Input SRAM and Output SRAM over a global bus of width $BW$ [2601.18070]. The tool’s scope is therefore broader than layer mapping alone. It treats mapping as inseparable from the physical allocation of compute and storage resources. ## 5. Mapping strategy space and search procedure in SRAM-CIM The SRAM-CIM version of CIM-Tuner uses a **two-level mapping strategy**. At the accelerator level, the spatial scheduling choices are: - **Non-Reversed (NR, weight-stationary)**: CIM weights hold the layer’s weights; input SRAM holds activation tiles. - **Reversed (R, input-stationary)**: CIM weights are reprogrammed each tile; input activation is stored in CIM. The temporal scheduling choices are: - **Input-Priority (IP)**: refill Input SRAM before re-programming CIM weights. - **Weight-Priority (WP)**: refill CIM weights first. At the macro level, the tiling choices are: - **Accumulation-First (AF)**, with $$ K_t = AL\times SCR,\qquad N_t = PC,\qquad M_t = MR, $$ bundling $SCR$ consecutive $AL$-sized $K$-chunks for the same output channel. - **Parallel-First (PF)**, with $$ K_t = AL,\qquad N_t = PC\times SCR,\qquad M_t = MR, $$ bundling $SCR$ consecutive $PC$-channels for the same input chunk. For a matrix multiplication $$ \mathbf{C}_{M\times N}=\mathbf{A}_{M\times K}\mathbf{B}_{K\times N}, $$ the numbers of macro-tiles are $$ N_M = \Bigl\lceil \frac{M}{M_t}\Bigr\rceil,\qquad N_N = \Bigl\lceil \frac{N}{N_t}\Bigr\rceil,\qquad N_K = \Bigl\lceil \frac{K}{K_t}\Bigr\rceil, $$ and the total macro invocations are $N_M\times N_N\times N_K$ [2601.18070]. Because there are 2 spatial choices, 2 temporal choices, and 2 tiling choices, the overall mapping strategy space per layer consists of **8 choices** [2601.18070]. The global search uses a **two-stage simulated annealing over $({\bf h},\pi)$**. The initialization sets ${\bf h}$ to the midpoint of the hardware search space, flattens all layers of equal $(M,N,K)$ into groups, and uses a temperature schedule $T_0\leftarrow T_{\rm init}$ with cooling rate $\alpha$ [2601.18070]. Each iteration then: 1. Proposes ${\bf h}'$ by randomly adjusting one of $\{MR,MC,SCR,IS\_SIZE,OS\_SIZE\}$. 2. Prunes ${\bf h}'$ if $Area({\bf h}')>A_{\max}$ or $ICW({\bf h}')