---
title: Catalyst Towers in Surface Codes
url: https://www.emergentmind.com/topics/catalyst-towers
type: topic
---

# Catalyst Towers in Surface Codes

Catalyst towers are a family of catalytic circuit gadgets for implementing arbitrary single-qubit $Z$-rotations in a surface-code architecture by exchanging additional ancilla qubits and routing area for reduced $T$-count, reduced $T$-depth, and shorter runtime. In the formulation analyzed in "Space and Time Cost of Continuous Rotations in Surface Codes" [2508.06236], catalyst towers appear in two principal variants—*in-circuit towers* and *independent towers*—and are evaluated not only at the level of asymptotic gate counts but also through explicit surface-code layouts, physical-qubit footprints, spacetime volume, and runtime in practical application settings.

## 1. Concept and theoretical basis

All catalyst-tower constructions in the cited treatment are based on the elementary *phase catalysis* gadget of Gidney and Fowler, which, given a single resource state $|R_z(2\theta)\rangle$ and a catalyst state $|R_z(\theta)\rangle$, applies two $R_z(\theta)$ rotations to arbitrary data qubits while perfectly recovering the catalyst. By chaining these gadgets in layers, one obtains a tower that amortizes the cost of producing or applying related rotations across a family of angles [2508.06236].

Two constructions are distinguished. *In-circuit towers* directly apply $\{R_z(2^i\theta)\}_{i=0}^{n-1}$ to data qubits at amortized cost
$$
T_{\text{in-circuit}}(n)=R_T+4n
$$
rather than $n\cdot R_T$ as in conventional gate synthesis. Here
$$
R_T \simeq 1.03\log_2(1/\epsilon)+5.75
$$
is the $T$-count of synthesizing one $R_z(2^n\theta)$ to error $\epsilon$. The stated trade-off is an increased measurement depth by $2n$.

*Independent towers* act as higher-level factories that consume $T$ states and produce a spectrum of resource states $\{|R_z(2^i\theta)\rangle\}_{i=0}^{n-1}$. Each rotation is then applied by RUS teleportation, with success probability $1/2$ per layer and angle doubling on failure. The expected teleportation depth scales only logarithmically in $n$, and both $T$-count and $T$-depth are asymptotically smaller than for serial gate synthesis [2508.06236].

The basic gate-complexity formulas are presented as:
$$
T_{\text{in}} = R_T + 4n,\qquad D_{\text{in}} = D_{\text{gate}} + 2n
$$
$$
T_{\text{gate}} = nR_T,\qquad D_{\text{gate}} \approx O(R_T)
$$
and, for independent towers with $L$ layers and $r$ repetitions,
$$
T_{\text{ind}}(L,r)=2LR_T+4(2L-1)+(r-1)[R_T+4(2L-1)]
$$
$$
D_{\text{ind}}(L)\approx R_T+2L.
$$

These expressions formalize the central design principle: catalyst towers replace repeated high-cost synthesis of related rotations with a structured catalytic process whose marginal cost grows more slowly, while shifting burden into ancilla provisioning, layout complexity, and routing.

## 2. Variants and operational mechanisms

The distinction between in-circuit and independent towers is architectural rather than merely algebraic. In-circuit towers are embedded directly in the computational circuit and apply the required rotation family in situ. Their main advantage is low amortized $T$-count relative to naively synthesizing each rotation independently. Their main limitation, as presented, is that the measurement depth increases linearly with the number of layers, so runtime improvements are not unconditional [2508.06236].

Independent towers externalize rotation preparation into separate factory-like subsystems. They generate a buffer of resource states that can subsequently be consumed via RUS teleportation. In the reported analysis, this shifts the design toward large-scale parallelism: data qubits can be arranged so that patch edges are exposed to either distillation factories or tower outputs, enabling massive parallel teleportation. The expected teleportation depth remains $O(\log n)$, which is the principal reason the independent construction can outperform standard Clifford+$T$ synthesis in runtime-sensitive regimes.

The paper also notes that, in both tower types, the corner notation of Gidney is used to represent Logical-AND gates. This places catalyst towers in a broader lineage of fault-tolerant constructions that use specialized logical gadgets to reduce non-Clifford overhead.

A common misconception is that lower $T$-count alone determines the superior implementation strategy. The analysis rejects this simplification explicitly: because towers require additional ancilla qubits and routing area, the cost function to optimize should be total runtime or total space rather than isolated $T$ metrics. This suggests that catalyst towers are best understood as space–time trade-off constructions, not universally dominant replacements for Clifford+$T$ synthesis.

## 3. Surface-code realization

The surface-code layouts are developed under a concrete implementation model: all logical qubits live on $d\times d$ patches, with Litinski’s lattice surgery and auto-corrected magic factories. This matters because the resource trade-offs are not abstract; they are tied to patch geometry, routing, and distillation throughput [2508.06236].

For *in-circuit towers* in the phase-oracle circuit, data qubits—described as copies of the input register—sit in two horizontal stripes. Each tower occupies 7 rows of patches per layer: four for catalyst and seed, two for Logical-AND ancillae, plus routing space. Magic factories, specifically AutoCCZ states, feed $T$ states into the tower via blue ancilla rectangles.

For *independent towers*, the layout is spatially decoupled from the data region. Independent towers are placed in a separate region around the data. Each $L$-layer tower requires approximately $4(6n_{\text{anc}}-2)$ logical patches, including routing, to produce the desired buffer of resource states. The data arrangement is chosen so that each patch edge is exposed to either a distillation factory or a tower output, enabling the cited large-scale parallel teleportation.

The implementation picture can be summarized as follows.

| Variant | Functional role | Layout characteristic |
|---|---|---|
| In-circuit tower | Applies $\{R_z(2^i\theta)\}$ directly to data qubits | 7 rows of patches per layer |
| Independent tower | Produces resource states for later teleportation | Separate region around the data |
| Conventional synthesis | Synthesizes rotations serially in Clifford+$T$ form | No tower-specific ancilla structure |

The significance of these layouts is methodological. They translate catalytic rotation schemes into explicit surface-code resource accounting, making comparison with conventional synthesis depend on physical architecture rather than only logical circuit identities.

## 4. Resource model and scaling laws

The cost model introduces physical-qubit and spacetime metrics that combine distillation demand with logical-patch occupancy. Let $N_T$ be the total $T$ states consumed by a subroutine of depth $t\cdot d$, and let $N_L$ be the number of logical qubits including ancillae. If a $T$-factory has footprint $N_{\text{fac}}$ qubits and latency $t_{\text{fac}}$ cycles, then the number of physical qubits for distillation is
$$
Q_{\text{dist}}(d)=\left\lceil \frac{N_T}{td}\right\rceil N_{\text{fac}},
$$
the data qubit footprint is
$$
Q_{\text{data}}(d)=2N_Ld^2,
$$
and total physical qubits are
$$
Q_{\text{tot}}(d)=Q_{\text{dist}}(d)+Q_{\text{data}}(d).
$$
The spacetime volume is
$$
V(d)=N_TN_{\text{fac}}t_{\text{fac}}+2N_Ltd^3,
$$
and, more generally,
$$
V(d,a,\theta)=\alpha(a,\theta)+\beta(a,\theta)d^3.
$$
The running time of the subroutine is approximated by
$$
R(d,a,\theta)\approx d\cdot D(d,a,\theta),
$$
where $D(d,a,\theta)$ is the measurement depth in code-time steps [2508.06236].

Within this model, the relevant depth scalings are:
- Clifford+$T$ synthesis: $D_{\text{gate}}=O(R_T)$, approximately 32 steps in the reported example.
- In-circuit tower: $D_{\text{in}}=D_{\text{gate}}+2n$.
- Independent tower: $D_{\text{ind}}\approx O(\log n)$, approximately 17 steps in the phase-oracle example.
- Hamming-weight phasing: $D_{\text{HW}}\sim N$ and $T_{\text{HW}}\sim N+O(\log N)$, with applicability restricted to parallel, identical angles.

This formulation shows why catalyst towers do not have a single monotone advantage. Lower $N_T$ can reduce factory demand, but increased $N_L$ raises the $d^2$ and $d^3$ terms. A plausible implication is that the dominant implementation changes with code distance because distillation savings and ancilla overhead scale differently.

## 5. Code-distance regimes and comparative performance

The reported resource comparisons identify three code-distance regimes in a phase-oracle circuit with $S=36$ pieces, $n=15$, and $l=\lceil \log_2 S\rceil =6$, using a $(15\to 1)_{11,5,5}$ factory with $N_{\text{fac}}=2070$ qubits, $t_{\text{fac}}=30$ cycles, and $p_{\text{phys}}=10^{-4}$ [2508.06236].

For this case, the logical-qubit counts are given as
$$
N_L^{\text{incirc}} = 7S(2n+l+2)+7(2n+3)
$$
for in-circuit towers, and
$$
N_L^{\text{indep}} = 5[(S+1)(2n+2)] + 4(6n+1)(S+1)+16S
$$
for independent towers.

The regime structure is explicit:

| Code-distance regime | Main conclusion |
|---|---|
| Small $d\lesssim 13$ | Independent towers achieve the lowest $V(d)$ |
| Medium $13\lesssim d\lesssim 16$ | Independent towers still halve runtime with modest $V$-overhead |
| Large $d\gtrsim 16$ | Conventional synthesis yields the smallest $V(d)$ and lowest $Q_{\text{tot}}$ |

The same section states that in-circuit towers always use the least $Q_{\text{data}}$ but run slower, with $D_{\text{in}}\approx 62$, and offer no volume reduction at large $d$.

These comparisons directly constrain generalization. Catalyst towers are not presented as asymptotically optimal in all regimes; rather, they are advantageous in specific fault-tolerant operating windows. The paper further emphasizes that larger $d$ suppresses the logical error rate,
$$
p_L(d)=0.1(100\,p_{\text{phys}})^{(d+1)/2},
$$
but also raises $V\propto d^3$ and $Q_{\text{data}}\propto d^2$. As a result, the $O(n)$ extra logical qubits per layer required by towers become increasingly expensive at large code distance.

## 6. Applications, trade-offs, and interpretation

Two practical application examples are used to ground the analysis: a parallel piecewise phase oracle for option pricing and a variational Gaussian-state preparation circuit [2508.06236].

For the phase-oracle case, the application summary reports:
- Conventional: $D\approx 32d$, $Q_{\text{tot}}(d=13)\approx 2.4\times 10^5$ qubits, $V\approx 1.0\times 10^9$ qubit·cycles.
- Independent towers: $D\approx 17d$, $Q_{\text{tot}}(d=13)\approx 2.7\times 10^5$ qubits, $V\approx 0.7\times 10^9$ qubit·cycles.
- Speedup of $1.9\times$ in runtime and a 30% reduction in volume at $d=13$.

For the Gaussian variational circuit, consisting of 60 copies of 35 $R_y$ rotations with $N_{\text{rot}}=2100$, the reported figures are:
- Canonical: $N_T\approx 53024$ per repetition, $D_{\text{gate}}\approx 177$.
- Independent control scheme: $N_T\approx 28709$, $D_{\text{ind}}\approx 39$.
- Independent excess scheme: $N_T\approx 45750$, $D_{\text{ind}}\approx 39$.

Assuming 300 logical data qubits plus routing in a 1:3 ratio and 4200 qubits to store RUS states, the paper states:
- For $d\lesssim 10$, the excess scheme uses the fewest physical qubits and is approximately $4.5\times$ faster than synthesis.
- For $d\gtrsim 10$, synthesis begins to win on space, though towers still cut runtime by a factor of approximately $4.5$.
- At $d=9$, the excess scheme uses approximately $1.2\times 10^5$ qubits versus $1.5\times 10^5$ for synthesis.

The main trade-off parameters are then listed explicitly: code distance $d$, ancilla overhead, $T$-factory choice, routing factor, and repetition count $r$. The dependence on repetition count is especially important: independent towers amortize startup cost only if the same $\theta$ is used many times, with amplitude estimation given as an example of a regime with $r\gg 1$.

A recurrent misunderstanding is that catalyst towers should replace conventional synthesis whenever continuous rotations are numerous. The reported evidence is narrower. The conclusions are sensitive to application scenarios and parameter choices, and conventional Clifford+$T$ synthesis may prove more efficient at large code distances. Conversely, catalyst towers may be particularly advantageous for early fault-tolerant quantum applications, where low and medium code distances are assumed and a spacetime trade-off is needed to reduce the runtime of individual circuit runs, especially in scenarios involving high circuit repetition counts [2508.06236].

Source: https://www.emergentmind.com/topics/catalyst-towers