---
title: 'AMS-IO-Agent: Design Automation for AMS ICs'
url: https://www.emergentmind.com/topics/ams-io-agent
type: topic
---

# AMS-IO-Agent: Design Automation for AMS ICs

AMS-IO-Agent is a domain-specialized large language model (LLM)-based agent framework for structure-aware input/output (I/O) subsystem generation in analog and mixed-signal (AMS) integrated circuits (ICs). Its central innovation is the translation of natural-language design intent into verified, industrial-grade AMS IC deliverables through integration of a structured domain knowledge base and a deterministic intent-structuring pipeline. AMS-IO-Agent is validated using the AMS-IO-Bench benchmark, achieving high rates of design rule check (DRC) and layout versus schematic (LVS) compliance, and has demonstrated direct silicon utilization in 28 nm CMOS fabrication [2512.21613]. The framework is seeded by the AMSNet dataset [2405.09045], which provides precise transistor-level schematic-netlist pairs and an automated conversion tool—enabling closed-loop, multimodal LLM workflows for advanced AMS I/O design.

## 1. System Architecture and Workflow

AMS-IO-Agent is organized as a modular pipeline bridging free-form pin-planning input to production-ready schematic/layout deliverables. The workflow consists of three primary modules and a middleware adaptor:

- **Design Intent Structuring**: Transforms ambiguous textual or tabular input (e.g., pin lists, layout requests) into a machine-readable “intent graph” encoding signal, pad order, device type, spatial position, connection hints, and corner cells using JSON.  
- **Intent Graph Adaptor**: Deterministically parses the intent graph, resolves geometric/numeric constraints (pad spacing, cell dimensions), computes physical coordinates, and emits Electronic Design Automation (EDA) scripts (SKILL for Cadence Virtuoso; csh for Calibre).
- **Domain-specific Knowledge Base**: A ∼6k-token repository encoding reusable constraints, device libraries, and design conventions (ESD cells, power-domain rules, naming patterns), loaded into the LLM’s context.

Final outputs consist of industrial-grade schematic/layout representations verified via DRC/LVS tools. The architecture enables robust separation of ambiguous, high-level design specification parsing (LLM-driven) from rule-based, deterministic physical code generation—mitigating typical reliability limitations of pure LLM synthesis [2512.21613].

## 2. Structured Domain Knowledge Base

AMS-IO-Agent employs a knowledge base (KB) encoded as JSON-formatted constraints and device libraries rather than static procedural rules. The KB supports robust enforcement of pad cell types, power domain separation, and layout spacing. A representative KB schema is:

| KB Attribute       | Example Entry                                       | Purpose                                  |
|--------------------|-----------------------------------------------------|------------------------------------------|
| pad_cell_types     | {digital: {width: 80 µm, min_spacing: 30 µm}}       | Enforce pad dimensions and spacing        |
| power_domains      | {VDD: {isolation_cell: iso_cell, min_iso: 50 µm}}   | Specify isolation between power domains   |
| constraints        | {min_width on M3: 0.2 µm, min_enclosure on M6: 0.1 µm}| Validate physical design rules           |
| corner_cells       | ["corner_ne", "corner_nw", "corner_sw", "corner_se"]| Ensure corner block insertion            |

The KB is queried during intent structuring and constraint resolution, supporting automatic insertion of correct pad dimensions, power-domain isolation, and compliance with physical design rules. *This suggests robust scalability to capture team-specific conventions and platform constraints* [2512.21613].

## 3. Design Intent Structuring and Code Generation

AMS-IO-Agent converts informal design specifications (text, spreadsheets) into precisely structured intent graphs (JSON), mapping signals, padding, directions, and cell attributes. An intent graph example:

```json
{
  "pads": [
    { "id": 1, "signal": "D0", "domain": "digital", "direction": "IN", "position": { "side": "TOP", "index": 1 } },
    ...
    { "id": 13, "signal": "VREFP", "domain": "analog", "direction": "IN", "position": { "side": "TOP", "index": 13 } }
  ],
  "corners": [
    { "position": "NE", "cell": "corner_ne" },
    { "position": "SE", "cell": "corner_se" }
  ]
}
```

Structured graphs are mapped into Python objects and further annotated based on signal inference rules. The adaptor module then parses and resolves all numeric constraints and emits SKILL/csh scripts for schematic and layout generation. This deterministic intermediate mapping prevents synthesis errors typical in end-to-end code outputs from LLMs.

*Editor’s term: “intent graph”* denotes the hierarchical, machine-readable representation of I/O and pad specifications prior to EDA code generation [2512.21613].

## 4. Benchmarking with AMS-IO-Bench

AMS-IO-Bench is a purpose-designed benchmark for evaluating I/O ring generation in wirebond-packaged AMS IC flows, sourced from 10 tape-outs and stratified into:

- Simple: single power domain, low pad count
- Medium: multi-domain, ~1 mm² single-row ring
- Hard: dual-row/staggered rings, custom cells, large outlines

Key quantitative metrics:

- **Intent Graph Pass Rate**: Fraction of cases correctly structured as intent graphs
- **Shape Validity (VLM)**: Vision-Language Model binary pass/fail of shape correctness
- **DRC Pass Rate**: Schematic/layout compliance with design rule checks
- **LVS Pass Rate**: Layout vs. schematic netlist matching
- **Combined DRC+LVS Pass Rate**
- **Turnaround Time Reduction**: \(S = \frac{T_{\text{baseline}}}{T_{\text{agent}}}\)

A plausible implication is that benchmarking across difficulty levels supports generalization claims for agent performance in both standard and custom AMS I/O scenarios [2512.21613].

## 5. Experimental Performance and Silicon Validation

Experimental evaluation on AMS-IO-Bench (30 cases; agent using Claude-3.7) demonstrates:

- Intent Graph and Shape Validity: 100%
- DRC Pass: 93.33% (28/30)
- LVS Pass: 76.67% (23/30)
- Combined DRC+LVS: 76.67%
- Mean Turnaround per Case: 4.2 minutes (vs. ~480 minutes for human baseline; vs. 0.2 minutes for GPT-4o baseline which fails DRC/LVS)

Baseline LLM models (direct code synthesis, GPT-4o) achieve 0% sign-off pass, indicating that structure-aware pipelining is a strict prerequisite for usable AMS IC outputs.

In silicon, a 28 nm mixed-signal prototype (1 mm × 1 mm, 48 pads) was taped-out with the agent-generated I/O ring. Layout changes (e.g., rapid pin-order change) were successfully applied with verified layout generation in minutes. Final chip passed DRC/LVS; electrical performance matched specification including leakage <1 nA and >100 MHz bandwidth for clock pads. *This suggests practical readiness for agent output integration into high-volume AMS IC workflows* [2512.21613].

## 6. Data Foundations and Multimodal Extensions via AMSNet

AMSNet is the enabling dataset for AMS-IO-Agent, containing 894 transistor-level circuit schematics paired with SPICE netlists. Circuits span current mirrors, amplifiers, bias generators, filters, and I/O buffers, with netlist complexity metrics: median device count ≈ 10, median net count ≈ 8. The dataset supports closed-loop, multimodal workflows by exposing schematic images and symbolic netlists, facilitating:

- Vision front-end (YOLO-based detection, >97% component accuracy, 96.7% net assignment accuracy)
- Schematic-to-netlist conversion via search routines and node assignment
- Machine-readable netlist and API with preview and batch usage

Potential training tasks are codified:
- Schematic-to-netlist translation (\(L_1=\operatorname{CrossEntropy}(\operatorname{tok}(N), \operatorname{Model}(S))\))
- Top-level netlist synthesis from block-level specifications, with simulation-driven loss (\(L_2\): weighted spec deviation)

This foundation supports reinforcement-learning loops and LLM fine-tuning for custom I/O modules, performance annotation via transistor sizing, and structured benchmarking [2405.09045].

## 7. Implications, Limitations, and Prospects

AMS-IO-Agent transforms AMS I/O design workflows by enabling rapid, error-resistant translation of natural-language and tabular specification into GDS/EDA deliverables. Contributions include substantially reduced manual layout time, late-cycle edit agility, and encapsulation of domain/team-specific conventions for broader accessibility.

Limitations are noted:
- Current focus is wirebond packaging and a KB tuned to a single node and flow
- Does not obviate expert review for highly custom or performance-critical cells

Future development directions include:
- Extension to flip-chip bump-pad rings, diverse packaging
- Integration with downstream routing and analog-verification toolchains
- Generalization of structured intent to regular analog layouts (e.g., DAC/ADC arrays)

A plausible implication is that the structured agent paradigm is extensible to many regular analog subsystems where domain constraints are highly codifiable [2512.21613][2405.09045].

Source: https://www.emergentmind.com/topics/ams-io-agent